Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
1999-11-29
2002-01-15
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C438S113000
Reexamination Certificate
active
06339251
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits and more particularly to methods and structures for reducing warping of integrated circuit wafers.
BACKGROUND OF THE INVENTION
As semiconductor integrated circuit devices have become more highly integrated to provide greater processing and/or memory capacity, chip sizes and deposition thickness have also increased. Accordingly, semiconductor wafer diameters have increased to provide increased numbers of the larger integrated circuit devices thereon. In other words, larger diameter semiconductor wafers can be used to fabricate larger numbers of integrated circuit devices.
The total thickness of layers deposited on semiconductor wafers may also increase because the more highly integrated devices may include a greater number of layers. Accordingly, more highly integrated devices may include a greater number of deposition, heat treatment, photolithography, and etching steps during the fabrication thereof, and the resulting stresses may cause the wafer to warp. In particular, depositions and thermal treatments at high temperatures of hundreds of degrees Celsius may stress the semiconductor wafer and cause warping.
For example, wafer warping has been observed during the fabrication of 64M dynamic random access memory (DRAM) devices, and wafer warping is likely to increase with higher capacity memory devices and with the use of larger diameter wafers. For example, when forming a polysilicon layer to provide gate electrodes for a DRAM, polysilicon layers may be formed on both the device side of the wafer and the backside of the wafer. Only the polysilicon layer on the device side of the wafer, however, is typically patterned so that differences in the stresses due to thermal expansion caused by the patterned and unpatterned polysilicon layers may cause wafer warping.
A technique for reducing warping is discussed in Japanese Patent Application No. 4-302432 which has been laid open. In the 4-302432 application, grooves are formed in the polysilicon layer on the backside of the wafer. Formation of these grooves, however, may make it difficult to hold the device side of the wafer even so that it is difficult to ensure focus margins during subsequent photolithography exposure steps. In other words, the grooves in the polysilicon layer on the backside of the wafer may make it difficult to support the wafer during photolithography exposure steps so that the device side of the wafer is maintained within a common focal plane. Furthermore, while this technique may reduce concave wafer warping, this technique may not address convex wafer warping.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide methods and structures that reduce wafer warping.
This and other objects are provided according to the present invention by forming first and second layers of a first material on opposing respective first and second faces of the semiconductor wafer, and removing the second layer of the first material from the second face of the semiconductor wafer. By removing the second layer, warping of the wafer can be reduced. More particularly, the first material can be polysilicon, and the first layer of the material can be patterned to form transistor gate electrodes for DRAM devices. By removing the second layer, thermal stress differences between a patterned and unpatterned polysilicon layers on opposing faces of a wafer can be reduced thereby reducing warping.
In addition, removal of the second layer can be followed by forming an electronic device on the first face of the semiconductor wafer. Furthermore, a plurality of electronic devices can be formed to provide a plurality of DRAM devices on the wafer. In addition, the formation of the first and second layers of the first material can be preceded by forming a gate oxide layer on the first face of the semiconductor wafer so that the first face of the semiconductor wafer and the first layer of the first material are separated by the gate oxide layer. The first layer of the first material and the gate oxide layer can then be patterned to form a plurality of transistor gate electrodes.
According to an alternate aspect of the present invention, a method of preparing a semiconductor wafer to reduce distortion thereof during the subsequent fabrication of integrated circuit devices is provided. In particular, grooves are formed in the device surface of the semiconductor wafer wherein the grooves are within scribe line regions of the semiconductor wafer. These grooves can reduce distortions in the wafer such as warping and convexing during the subsequent formation of integrated circuit devices on the wafer.
The methods and structures of the present invention can thus reduce warping of semiconductor wafers during the fabrication of integrated circuit devices thereon.
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Choi Jin-Kee
Ha Min-Seok
Jeong Cheol
Chaudhuri Olik
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co. LTD
Wille Douglas A.
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