Wafer fabrication of inside-wrapped contacts for electronic devi

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438118, 438124, 438462, 438613, H01L21/44;21/48;21/50

Patent

active

059044969

ABSTRACT:
A packaging technique for electronic devices includes wafer fabrication of contacts that wrap down the inside surface of a substrate post. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. A trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold beam wire extends from a connection point within the circuit into the trench. Unless an insulative substrate is used, the wire runs over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back planed to form the bottom surface of the post. Then it is selectively back etched, to expose the bottom surface of the wire, to form the inside surface of the post, and to form the bottom surface of the finished device. A solderable lead wire runs from the exposed gold wire, down the inside surface of the post, and across its bottom. Sawing forms the outside surface of the post and completes the finished device without subsequent assembly. Alternatively, no post is used and the contact comprises an encapsulant protrusion, similarly formed in a silicon trench that is subsequently etched away. Gold wires run under the protrusion and may be covered by solderable metal, or a dense gold compression bond may be used. Optionally, the bottom of the finished device drops down to be co-planar with the contact bottoms, so as to conduct heat out of the device.

REFERENCES:
patent: 4783695 (1988-11-01), Eichelberger et al.
patent: 4835704 (1989-05-01), Eichelberger et al.
patent: 4931410 (1990-06-01), Tokunaga et al.
patent: 5071792 (1991-12-01), Van Vonno et al.
patent: 5161093 (1992-11-01), Gorczyca et al.
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5407864 (1995-04-01), Kim
patent: 5434745 (1995-07-01), Shokrgozar et al.
patent: 5521420 (1996-05-01), Richards et al.
patent: 5557149 (1996-09-01), Richards et al.
patent: 5559362 (1996-09-01), Narita
patent: 5595935 (1997-01-01), Chan et al.
patent: 5639694 (1997-06-01), Diffenderfer et al.
PCT International Search Report.
"Joint Industry Standard Implementation of Flip Chip and Chip Scale Technology," The Institute for Interconnecting and Packaging Electronic Circuits (Jan. 1996).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Wafer fabrication of inside-wrapped contacts for electronic devi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer fabrication of inside-wrapped contacts for electronic devi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer fabrication of inside-wrapped contacts for electronic devi will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1755293

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.