Wafer expansion-and-contraction simulating method

Details Wafer expansion-and-contraction simulating method Wafer expansion-and-contraction simulating method

1998-03-26

2000-11-07

Stamber, Eric W.

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

257633, G06F 1750

Patent

active

061449318

ABSTRACT:
A wafer expansion-and-contraction simulation method in which stress (intrinsic stress) caused in a film forming process on a wafer is taken into consideration, the calculation time can be shorten, and a storage amount of data can be reduced. In the simulation method, an elastic thermal stress simulation when the temperature of the silicon wafer is increased from the room temperature to the film forming temperature is performed, and the displacement of the wafer thus obtained is reserved. Thereafter, an elastic thermal stress simulation when the temperature of the silicon wafer coated with the thin film is decreased from the film forming temperature to the room temperature is performed, and the displacement of the wafer thus obtained is reserved. In the simulation, thermal strain is uniformly applied to the thin film as corresponding to an intrinsic stress in the film forming process. Finally, the displacement values in the respective steps are added to obtain the total displacement due to the expansion and contraction of the wafer in the film forming process.

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