Wafer edge sealing

Details Wafer edge sealing Wafer edge sealing

1995-12-18

1997-04-08

Powell, William

Semiconductor device manufacturing: process

With measuring or testing

438703, 438761, H01L 2100

Patent

active

056183801

ABSTRACT:
A method and process for reducing edge-related defects. The present invention comprises the steps of calibrating multiple process units such that the multiple process units are equally referenced with respect to an edge of a semiconductor wafer. The calibrated multiple process units are then utilized to precisely control respective termination distances of deposited substrate layers with respect to the edge of the semiconductor wafer. Furthermore, the deposited substrate layers are selectively stacked in manner which prevents semiconductor wafer edge-related defects. In so doing, the present claimed invention increases semiconductor device yields.

REFERENCES:
Hause et al., "Yield Improvement by Wafer Edge Engineering", SPIE vol. 2635, at 22-29, Aug. 1995.

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