Wafer dividing method

Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Substrate dicing

Reexamination Certificate

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Details

C438S068000, C438S458000

Reexamination Certificate

active

11167848

ABSTRACT:
A wafer processing method of dividing a wafer having function elements formed in areas sectioned by dividing lines formed on the front surface in a lattice pattern, into individual chips along the dividing lines, which comprises a deteriorated layer forming step for forming a deteriorated layer in the inside of the wafer along the dividing lines; a wafer supporting step for putting the back surface of the wafer on an extensible support tape mounted on an annular frame; and a dividing step for dividing the wafer along the dividing lines by expanding the support tape affixed to the wafer, wherein the dividing step comprises first dividing the wafer along dividing lines extending in a predetermined direction and subsequently, along dividing lines extending in a direction intersecting with the predetermined direction by expanding the support tape such that tensile force acting in a direction perpendicular to the dividing lines extending in the predetermined direction becomes larger than tensile force acting in a direction perpendicular to the dividing lines extending in the direction intersecting with the predetermined direction, when the supporting tape affixed to the wafer is expanded.

REFERENCES:
patent: 6803320 (2004-10-01), Yamamoto
patent: 6939785 (2005-09-01), Kajiyama et al.
patent: 7179722 (2007-02-01), Murata et al.
patent: 2005/0090077 (2005-04-01), Nagai et al.
patent: 2005/0170613 (2005-08-01), Murata et al.
patent: 2005/0170616 (2005-08-01), Murata et al.
patent: 2005/0259459 (2005-11-01), Nagai et al.
patent: 2005/0282359 (2005-12-01), Nagai et al.
patent: 2002-192370 (2002-07-01), None
patent: 3408805 (2003-03-01), None
patent: 2005-129607 (2005-05-01), None

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