Wafer dicing process for optical electronic packing

Details Wafer dicing process for optical electronic packing Wafer dicing process for optical electronic packing

2007-11-13

2007-11-13

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

C438S458000, C438S113000, C257SE23009

Reexamination Certificate

active

11328094

ABSTRACT:
A wafer dicing process for optical electronic packing is provided. The process includes: providing a first wafer (glass wafer) and a second wafer (interposer wafer); etching the second wafer to form a reference flat coordinate; laminating the first wafer on the second wafer; providing a third wafer (CMOS wafer); laminating the third wafer under the second wafer; cutting the first wafer by a first dicing saw according to the reference flat coordinate; and cutting the third wafer by a second dicing saw to form a first reference axis and a second reference axis perpendicular to each other and to establish a backside dicing reference coordinate. The process not only can reduce wearing loss of the dicing saws but also ensure to form high quality cutting edges and a precise backside dicing reference coordinate.

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patent: 2005/0042844 (2005-02-01), Yee
patent: 2006/0121693 (2006-06-01), Yang et al.

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