Wafer dicing method

Semiconductor device manufacturing: process – Semiconductor substrate dicing – With attachment to temporary support or carrier

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S460000, C438S462000, C257SE21599

Reexamination Certificate

active

07598157

ABSTRACT:
A wafer stacked on a mounting layer is safely diced. The mounting layer has holes partially corresponding to chips on the wafer. Thus, chips obtained after dicing the wafer can be safely removed from the mounting tape. An amount of the mounting tape used can be reduced. And a production cost can be lowered as well.

REFERENCES:
patent: 4296542 (1981-10-01), Gotman
patent: 5362681 (1994-11-01), Roberts et al.
patent: 6563204 (2003-05-01), Glenn
patent: 2007/0275544 (2007-11-01), Maki et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Wafer dicing method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer dicing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer dicing method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4067470

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.