Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-06-14
2001-08-28
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000
Reexamination Certificate
active
06281128
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a semiconductor wafer polishing apparatus and, more specifically, to a semiconductor wafer carrier having an intersecting relieved surface to reduce the probability of wafer breakage during unloading.
BACKGROUND OF THE INVENTION
In the fabrication of semiconductor components, various devices are formed in layers upon an underlying substrate that is typically composed of a semiconductor material, such as silicon. The various discrete devices are interconnected by metal conductor lines to form the desired integrated circuits. The metal conductor lines are further insulated from the next interconnection level by thin films of insulating material deposited by, for example, CVD (Chemical Vapor Deposition) of oxide or application of SOG (Spin On Glass) layers followed by fellow processes. Holes, or vias, formed through the insulating layers provide electrical connectivity between successive conductive interconnection layers. In such microcircuit wiring processes, it is desirable that the insulating layers have a smooth surface topography, since it is difficult to lithographically image and pattern layers applied to rough surfaces.
Conventional chemical/mechanical polishing (CMP) has been developed for providing smooth semiconductor topographies. Chemical/mechanical polishing (CMP) can be used for planarizing: (a) insulator surfaces, such as silicon oxide or silicon nitride, deposited by chemical vapor deposition; (b) insulating layers, such as glasses deposited by spin-on and reflow deposition means, over semiconductor devices; or (c) metallic conductor interconnection wiring layers. Semiconductor wafers may also be planarized to: control layer thickness, sharpen the edge of via “plugs”, remove a hardmask, remove other material layers, etc. Significantly, a given semiconductor wafer may be planarized several times, such as upon completion of each metal layer. For example, following via formation in a dielectric material layer, a metalization layer is blanket deposited and then CMP is used to produce planar metal studs.
Briefly, the CMP process involves holding and rotating a thin, reasonably flat, semiconductor wafer against a rotating polishing surface. The polishing surface is wetted by a chemical slurry, under controlled chemical, pressure, and temperature conditions. The chemical slurry contains a polishing agent, such as alumina or silica, which is used as the abrasive material. Additionally, the slurry contains selected chemicals which etch or oxidize selected surfaces of the wafer during processing. The combination of mechanical and chemical removal of material during polishing results in superior planarization of the polished surface. In this process it is important to remove a sufficient amount of material to provide a smooth surface, without removing an excessive amount of underlying materials. Accurate material removal is particularly important in today's submicron technologies where the layers between device and metal levels are constantly getting thinner.
One problem area associated with chemical/mechanical polishing is in the step of removing the planarized wafer from the wafer carrier in which it is held for polishing without damaging the wafer. The wafers are temporarily stored in deionized (DI) water while awaiting CMP or further processing. With the inner face of the wafer carrier wetted by DI water and the semiconductor wafer in contact with the inner face, the DI water creates a capillary adhesion force between the semiconductor wafer and the wafer carrier. As the CMP process proceeds, all gases, e.g., air, are expelled from between the wafer and the wafer carrier inner face. The resultant effect is the formation by adsorption of a thin film between the surface of the wafer carrier and the surface of the wafer. The DI water film adheres to the surfaces of both the semiconductor wafer and the wafer carrier. Thus, when the CMP process is complete and the wafer is to be returned to a storage location, the semiconductor wafer clings to the wafer carrier. It is necessary to break the seal between the wafer and the wafer carrier without damaging the wafer. Conventional eight inch wafer carriers, such as those associated with a SpeedFam polisher tool #9206) have two fluid draining grooves of approximately 0.25″ width in a cruciform pattern about the center of the cup. Thus, the relieved area in which adhesion cannot occur is about eight percent (~4 in
2
/~50 in
2
=0.08) of the total cup surface area. Experience has shown that this configuration requires excessive force to “break” the adhesion between the wafer and the wafer carrier, resulting in wafer breakage. This is, of course, highly undesirable because of the cost associated with the lost production cost associated with such breakage.
Accordingly, what is needed in the art is an improved wafer carrier design that minimizes semiconductor wafer breakage while reducing unload cycle time.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a wafer carrier for use with a semiconductor wafer polishing apparatus. In one embodiment, the wafer carrier comprises a carrying head having opposing first and second surfaces, a primary channel system formed in the second surface, and a secondary channel system formed in the second surface. The first surface is coupleable to the semiconductor polishing apparatus and the second surface is adapted to receive a semiconductor wafer to be polished. The primary channel system comprises first and second intersecting channels. The secondary channel system intersects the primary channel system so that the secondary channel system and the primary channel system cooperate to occupy a substantial portion of a surface area of the second surface. Therefore, the primary channel system and the secondary channel system decrease an amount of force required to remove the semiconductor wafer from the second surface.
In an alternative embodiment, the primary channel system is a cruciform channel system and the first and second intersecting channels each have a width of about 12 percent of a diameter of the second surface. In another embodiment, the wafer carrier further comprises a third channel system that intersects the primary and secondary channel systems.
The secondary channel system may be an annular channel, and in one particular aspect, an inner radius of the annular channel is about 12 percent of a diameter of the second surface and an outer radius is about 45 percent of the diameter.
In yet another embodiment, the substantial portion is greater than about 50 percent of the surface area, which provides a greater channeling area for the fluid and, thereby, reduces the amount of force required to break the seal between the carrier surface and the wafer, which is formed by the fluid. Alternatively, the substantial portion may be about 85 percent of the surface area. The primary channel system and the secondary channel system, in another embodiment, may be about 0.251″ deep.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 5695392 (1997-12-01), Kim
patent: 5788560 (2000-08-01), Hashimoto et al.
patent: 5814240 (1998-09-01), Yamashita
patent: 6080049 (2000-06-01), Numoto et al.
patent: 6089961 (2000-07-01), Cesna et al.
patent: 6102779
Maury Alvaro
Maze John A.
Miceli Frank
Rodriguez Jose Omar
Symons Robert M.
Agere Systems Guardian Corp.
Deo Duy-Vu
Kunemund Robert
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