Wafer burn-in testing method

Details Wafer burn-in testing method Wafer burn-in testing method

1998-04-22

2002-05-07

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S760020, C324S765010, C324S757020, C324S758010

Reexamination Certificate

active

06384613

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial No. 87102080, filed Feb. 16, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a wafer burn-in testing method. More particularly, the present invention relates to a wafer burn-in testing method for testing all the components in a wafer.
2. Description of Related Art
FIG. 1
is a simplified diagram showing the manufacturing of an integrated circuit chip from a silicon wafer to final packaging. As shown in
FIG. 1
, after a series of steps for fabricating integrated circuits on a semiconductor wafer, a circular wafer
2
having a cut-away edge originally for facilitating alignment is produced. Because wafer fabrication produces a large number of individual chips
4
whose electrical properties may vary considerably, each of these chips
4
needs to be tested electrically. In general, a plurality of bonding pads
6
is formed on the periphery of each chip serving as testing points and/or subsequent connection. These bonding pads
6
can be used for testing the chips in two ways. First, before the wafer is cut up into individual dies or chips, mechanical probes can be used to form electrical contact with the bonding pad. Therefore, each chip
4
within the wafer can be individually electrically tested. Alternatively, after the wafer is cut into individual chips
8
, wires can be bonded to the bonding pads
6
. Then, the whole chip
8
can be enclosed within a package
10
, and finally an integrated circuit (IC) package
12
or a large-scale integration (LSI) is formed. Electrical testing of the chip
8
can be carried out with ease after a complete package is formed because automatic testing machines can tap from the fixed external terminals and conduct the burn-in testing.
To connect from the bonding pads of a wafer chip to external terminals, a medium such as a wire or a bump must be used.
FIG. 2
is a diagram showing a wire bonding method of connecting from the bonding pads on a wafer chip to external packaging.
FIG. 3
is a diagram showing a tape-automated bonding (TAB) method of connecting from the bonding pads on a wafer to external packaging.
FIG. 4
is a diagram showing a flip chip (FC) method of connecting from the bonding pads on a wafer to external packaging. In the wire bonding method as in
FIG. 2
, a piece of fine metallic wire is used to connect one of the bonding pads on the wafer chip to an external metal lead. In the tape-automated bonding method shown in
FIG. 3
, a piece of tape is used for connecting a bump on a bonding pad of a wafer chip to an external metal lead. In the flip chip (FC) method shown in
FIG. 4
, a solder bump between a bonding pad and a circuit film is used to connect the wafer chip to the external metallic terminals.
FIGS. 5A through 5G
are cross-sectional views showing the progression of manufacturing steps needed to produce a bump. First, as shown in
FIG. 5A
, passivation layers
22
are formed on each side of aluminum bonding pad
20
. Next, as shown in
FIG. 5B
, a titanium (Ti) layer
24
having a thickness of about 1000 Å is formed over the aluminum pad
20
and the passivation layers
22
. Thereafter, a copper (Cu) layer
26
having a thickness of about 4000 Å is formed over the titanium layer
24
. Then, as shown in
FIG. 5C
, a photoresist layer
28
having a thickness of between 30 &mgr;m to 40 &mgr;m is formed over the copper layer
26
. Subsequently, using a mask
32
having chromium pattern
30
on it, a portion of the photoresist layer
28
is exposed to ultraviolet (UV) light. In the subsequent step, as shown in
FIG. 5D
, the exposed photoresist layer
28
is removed by etching to form a trench
34
. After that, as shown in
FIG. 5E
, a layer of copper
36
with a thickness of about 8 &mgr;m is first deposited into the trench
34
. Next, either lead-tin (SnPb) or gold (Au) solder is poured into the trench
34
forming a mushroom-shaped structure
38
. Later, as shown in
FIG. 5F
, the photoresist layer
28
on each side of the mushroom-shaped lead-tin solder
38
is removed. Finally, as shown in
FIG. 5G
, a bump with a hemispherical-shaped upper profile is formed after further chemical treatment.
FIG. 6
shows the general IC layout for carrying out conventional burn-in testing. As shown in
FIG. 6
, a chip
48
in the middle is connected to external terminals for testing through a back plate
40
containing testing pads
42
, inner-leads
44
, outer-leads
46
and outer-leads holes
50
. Therefore, a high-quality IC or LSI is obtained by first sawing the fabricated wafer into dies, then forming each die into a package, and finally the packaged product has to pass a burn-in test. The above procedure for obtaining a good die is known commonly as a known good die (KDG) method. Although the KDG method can obtain highly functional packages, the testing cost is exceptionally high because each chip has to be tested individually. Moreover, whenever a defect is found during testing, the whole package has to be scrapped leading to more waste due to cost spent on packaging.
In light of the foregoing, there is a need for a better burn-in testing method for wafers.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a method for testing the whole wafer so that defective wafer chips are detected and scrapped before the wafer is used for packaging. Hence, packaging cost can be saved and yield of packaged IC can be increased considerably.
In another aspect, this invention provides a method for testing the whole wafer by meshing the bonding pads on a tape-automated bonding (TAB) tape with bumps on the wafer so that complicated circuits can be avoided. In other words, the capacity to design two or more layers of internal circuits on a TAB tape is utilized such that internal circuits for carrying out the burn-in testing of the whole wafer can be greatly simplified.
In yet another aspect, this invention provides some tooling (fixtures) and a mechanism (suction caused by drawing a vacuum) for tightly engaging the bumps on the wafer with the pads on the TAB tape. Moreover, when the burn-in testing is finished, the TAB tape and the tooling can be used repeatedly for checking other wafers, one at a time. Therefore, the cost of operation is reduced to a minimum.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for carrying out wafer burn-in testing. The method comprises the steps of first providing a wafer and then forming a plurality of bumps on the wafer. Next, a tape-automated bonding (TAB) tape having a plurality of bonding pads is designed and fabricated. Each bonding pad has an external contact point and is electrically connected with an internal circuit. Pressure is applied to the wafer so that the bumps on the wafer can make contact with the bonding pads on the TAB tape. Subsequently, voltages and currents can be supplied to various bonding pads through the tape to carry out burn-in testing necessary for the whole wafer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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