Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-10-21
2001-10-02
Nguyen, Vinh P. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090
Reexamination Certificate
active
06297658
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a wafer burn-in cassette for performing a simultaneous burn-in process with respect to a plurality of semiconductor integrated circuit elements (hereinafter referred to as semiconductor chips) formed in a semiconductor wafer and to a method of manufacturing a probe card for use in the wafer burn-in cassette.
In the process of fabricating a conventional semiconductor integrated circuit device, an electrical connection is provided between a semiconductor chip and a leadframe by a bonding wire and then the semiconductor chip and the leads of the leadframe are sealed with a resin or ceramic to be mounted on a printed circuit board.
To meet the demand for an electronic device reduced in both size and price, there has been developed a method of mounting, on a circuit board, a semiconductor integrated circuit device as a bare chip cut out of a semiconductor wafer. The bare chip used in the method is preferably a quality-assured bare chip supplied at lower price.
For the quality assurance of a bare chip, it is required to perform a simultaneous burn-in process with respect to a plurality of semiconductor chips formed in a semiconductor wafer and thereby test the semiconductor chips for electric characteristics.
To satisfy the requirement, there has been proposed a wafer burn-in cassette as disclosed in U.S. Pat. application Ser. No. 08/358609, which comprises: a wafer tray for holding a semiconductor wafer formed with a plurality of semiconductor chips; a probe card disposed in opposing relation to the semiconductor wafer held by the wafer tray and having bumps to be connected to the respective external terminals of the semiconductor chips of the semiconductor wafer; and an annular sealing member disposed between the wafer tray and the probe card to define a sealed space in combination with the wafer tray and the probe card.
Referring to
FIGS. 10 and 11
, the foregoing wafer burn-in cassette will be described.
FIG. 10
shows the cross-sectional structure of the wafer burn-in cassette.
FIG. 11
shows the partially enlarged cross-sectional structure of the wafer burn-in cassette.
As illustrated in
FIG. 10
, the wafer tray
11
holding a semiconductor wafer
10
and a wiring board
13
holding an elastic probe card
12
made of a polyimide resin are disposed in opposing relation to each other. On the other hand, an annular sealing member
14
is formed around the perimeter of the wafer tray
11
. When the wafer tray
11
and the probe card
12
are brought closer to each other, a first sealed space
15
is defined by the wafer tray
11
, the probe card
12
, and the sealing member
14
.
As illustrated in
FIG. 11
, each of the semiconductor chips formed in the semiconductor wafer
10
has an electrode pad
16
.
As illustrated in
FIGS. 10 and 11
, bumps
17
are provided on the portions of the probe card
12
corresponding to the electrode pads
16
of the semiconductor chips in the semiconductor wafer
10
, while the peripheral portion of the probe card
12
is held by a rigid ring
18
. Isolated patterns
19
composed of, e.g., copper are formed on the side of the probe card
12
opposite to the bumps
17
to be integral with the bumps
17
. Since the probe card
12
is held between the bumps
17
and the isolated patterns
19
, the bumps
17
and the isolated patterns
19
never fall out of the probe card
12
.
As illustrated in
FIG. 11
, the wiring board
13
is provided with multilayer wiring
20
having one terminal connected to a test system (not shown) for supplying a test voltage such as a power-source voltage, ground voltage, or signal voltage and with anisotropic conductive rubber
21
for electrically connecting the other terminal of the multilayer wiring
20
to the bumps
17
.
As illustrated in
FIG. 10
, a valve
22
connected to evacuating means (not shown) is provided in a side face of the wafer tray
11
, while an annular groove
23
connected to the first sealed space
15
and to the valve
22
is formed in the top face of the wafer tray
11
to be interposed between the semiconductor wafer
10
and the sealing member
14
.
When the valve
22
is connected to the evacuating means to evacuate the first sealed space
15
, the wafer tray
11
and the probe card
12
are brought much closer to each other than in
FIG. 10
, so that electrical connections are provided between the respective electrode pads
16
of the semiconductor chips in the semiconductor wafer
10
and the corresponding bumps
17
of the probe card
12
. Thereafter, the electric characteristics of the semiconductor chips are evaluated by using the test system which applies the test voltage to each of the semiconductor chips in the semiconductor wafer
10
and receives an output signal from each of the semiconductor chips.
While the evacuation of the first sealed space
15
has thus brought the wafer tray
11
and the probe card
12
much closer to each other and provided electrical connections between the respective electrode pads
16
of the semiconductor chips in the semiconductor wafer
10
and the corresponding bumps
17
of the probe card
12
, it also produces a pressure difference between the first sealed space
15
and a second sealed space
25
defined by the probe card
12
and the anisotropic conductive rubber
21
of the wiring board
13
. On the other hand, the probe card
12
having elasticity is pulled toward the first sealed space
15
to be partially in contact with the semiconductor wafer
10
and the wafer tray
11
, as shown in FIG.
12
.
However, since the distance between each of the bumps
17
and the sealing member
14
over the probe card
12
is larger than the distance between the adjacent bumps
17
over the probe card
12
, the region of the probe card
12
extending between the bumps
17
and the sealing member
14
is elongated to a greater degree than the region of the probe card
12
extending between the adjacent bumps
17
. As a result, the bumps
17
disposed on the peripheral portion of the probe card
12
move outwardly toward the sealing member
14
, which causes the first problem that electrical connections are less likely to be achieved between the bumps
17
and the electrode pads
16
of the semiconductor wafer
10
.
Although the difference between the distance between each of the bumps
17
and the sealing member
14
over the probe card
12
and the distance between the adjacent bumps
17
over the probe card
12
is reduced by inwardly shifting the position of the sealing member
14
toward the bumps
17
on the peripheral portion, it is impossible to prevent the region extending between the sealing member
14
and the bumps
17
from being elongated to a greater degree than the region of the probe card
12
extending between the adjacent bumps
17
due to the level difference equivalent to the thickness of the semiconductor wafer
10
, which is observed on the peripheral portion of the wafer tray
11
.
Moreover, the probe card
12
held between the bumps
17
and the isolated patterns
19
cannot be elongated in the region in which the isolated patterns
19
are formed densely but is elongated only in the region in which the isolated patterns
19
are formed coarsely. Accordingly, the internal stress acting on the probe card
12
is increased in the region with the dense isolated patterns
19
, while it is reduced in the region with the coarse isolated patterns
19
, so that the bumps
17
on the probe card
12
are pulled toward the region with the dense isolated patterns
19
. As a result, the bumps
17
on the probe card
12
lying between the region with the dense isolated patterns
19
and the region with the coarse isolated patterns
19
move toward the region with the dense isolated patterns
19
, which causes the second problem that electrical connections are less likely to be achieved between the bumps
17
and the electrode pads
16
of the semiconductor wafer
10
.
SUMMARY OF THE INVENTION
In view of the foregoing, it is therefore a first object of the present invention to prevent t
Nakata Yoshiro
Oki Shinichi
Matsushita Electric - Industrial Co., Ltd.
Nguyen Vinh P.
Nixon & Peabody LLP
Patel Paresh
Robinson Eric J.
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