Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
2006-05-02
2006-05-02
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S106000, C438S107000, C438S109000, C438S457000, C438S459000
Reexamination Certificate
active
07037804
ABSTRACT:
A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.
REFERENCES:
patent: 4607779 (1986-08-01), Burns
patent: 4689113 (1987-08-01), Balasubramanyam et al.
patent: 5241450 (1993-08-01), Bernhardt et al.
patent: 5366908 (1994-11-01), Wolnalrowski et al.
patent: 5401672 (1995-03-01), Kurtz et al.
patent: 5419806 (1995-05-01), Huebner
patent: 5455445 (1995-10-01), Kurtz et al.
patent: 5473197 (1995-12-01), Idaka et al.
patent: 5545281 (1996-08-01), Matsui et al.
patent: 5627106 (1997-05-01), Hsu
patent: 5656554 (1997-08-01), Desai et al.
patent: 5773986 (1998-06-01), Thompson et al.
patent: 5880010 (1999-03-01), Davidson
patent: 5886535 (1999-03-01), Budnaitis
patent: 5998808 (1999-12-01), Matsushita
patent: 6100181 (2000-08-01), You et al.
patent: 6238951 (2001-05-01), Caillat
patent: 6255726 (2001-07-01), Vindasius et al.
patent: 6297072 (2001-10-01), Tilmans et al.
patent: 6340608 (2002-01-01), Chooi et al.
patent: 6485824 (2002-01-01), Kodama et al.
patent: 6355501 (2002-03-01), Fung et al.
patent: 6355976 (2002-03-01), Faris
patent: 6373130 (2002-04-01), Salaville
patent: 6461890 (2002-10-01), Shibata
patent: 6468098 (2002-10-01), Eldridge
patent: 6504253 (2003-01-01), Mastromatteo et al.
patent: 6559042 (2003-05-01), Barth et al.
patent: 6583512 (2003-06-01), Nakaoka et al.
patent: 6594025 (2003-07-01), Forouhi
patent: 6643920 (2003-11-01), Hori
patent: 6724084 (2004-04-01), Hikita et al.
patent: 2002/0024628 (2002-02-01), Walker et al.
patent: 2002/0163072 (2002-11-01), Gupta et al.
patent: 2003/0079836 (2003-05-01), Lin et al.
patent: WO008804829 (1988-06-01), None
“Ultra Thin Electronics for Space Applications”, 2001 Electronic Components and Technology Conference, 2001 IEEE.
“Copper Wafer Bonding”; A. Fan, A. Rahman, and R. Reif; Electrochemical and Solid-State Letters, 2 (10) 534-536 (1999).
“Face to Face Wafer Bonding for 3D Chip Stack Fabrication to Shorten Wire Lengths”, Jun. 27-29, 2000 VMIC Conference 2000 IMIC—200/00/0090(c).
“InterChip Via Technology for Vertical Systems Integration”, Fraunhofer Institute for Reliability and Microintegration, Munich, Germany; Infineon Technologies AG, Munich, Germany; 2001 IEEE.
Kellar Scot A.
Kim Sarah E.
List R. Scott
Beale Jay P.
Owens Beth E.
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