Wafer and method of making same

Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

361414, 357 2, 357 6, H05K 114

Patent

active

048477320

ABSTRACT:
Disclosed is a wafer substrate for integrated circuits 1 which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal 19,20, thus providing two principal levels of interconnection. A programmable amorphous silicon insulation layer 21 is placed between the metal layers. There are sheet lower metal layers with an insulator which permit power distribution across the wafer. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layers or layers, respectively. Pedestals are provided for bonding.

REFERENCES:
patent: 3699543 (1972-10-01), Neale
patent: 3781683 (1973-12-01), Freed
patent: 3983479 (1976-09-01), Lee et al.
patent: 4021838 (1977-05-01), Warwick
patent: 4047132 (1977-09-01), Krajiwski
patent: 4074342 (1978-02-01), Honn et al.
patent: 4115872 (1978-09-01), Bluhm
patent: 4146902 (1979-03-01), Tanimoto et al.
patent: 4174521 (1979-11-01), Neale
patent: 4177475 (1979-12-01), Holmberg
patent: 4257061 (1981-03-01), Chapel, Jr. et al.
patent: 4366614 (1983-01-01), Kumurdjian
patent: 4420766 (1983-12-01), Kasten
patent: 4433342 (1984-02-01), Patel et al.
patent: 4441249 (1984-04-01), Alspecter et al.
patent: 4453176 (1985-06-01), Chance et al.
patent: 4458297 (1984-07-01), Stopper et al.
patent: 4467400 (1984-08-01), Stopper
patent: 4471374 (1984-09-01), Hardee et al.
patent: 4471376 (1984-09-01), Morcom et al.
patent: 4479088 (1984-10-01), Stopper
patent: 4481283 (1984-11-01), Kerr et al.
patent: 4484215 (1984-11-01), Pappas
IBM, Technical Disclosure, vol. 22, No. 8A, Jan. 1980.
Hallas et al., Test Structure for Semiconductor Chips IBM Technical Disclosure Bulletin, vol. 19, No. 3, Aug. 1976.
Ghatalia et al., Semiconductor Process Defect Monitor, IBM Technical Disclosure Bulletin, vol. 17, No. 9, Feb. 1975.
Pluggable-Module Power-Connection Mechanism IBM Technical Disclosure Bulletin, vol. 27, No. 10A, Mar. 1985.
Archey et al., Integrated Magnetic Memory Structure, IBM Technical Disclosure Bulletin, vol. 14, No. 7, Dec. 1971.
Thick Film Integrated Decoupling Capacitor With Redundancy, IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr. 1985.
Davidson et al., Capacitor For Multichip Modules, IBM Technical Disclosure Bulletin, vol. 20, No. 8, Jan. 1978.
Bodendorf et al., Active Silicon Chip Carrier, IBM Technical Disclosure Bulletin, vol. 15, No. 2, Jul. 1972, pp. 656-657.
Article entitled "Thermal-Conduction Module Cradles and Cools Up to 133 LSI Chips", by D. R. Barbour, O. Oktay and R. A. Rinne, Electronics, Jun. 16, 1982, pp. 143-146.
Article entitled "Amorphous Vias in Wafer Link Chips", from Electronics, Sep. 22, 1983, pp. 48 and 49.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Wafer and method of making same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer and method of making same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer and method of making same will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-441207

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.