Wafer alignment system

Details Wafer alignment system Wafer alignment system

2000-08-30

2004-03-16

Barlow, John (Department: 2863)

Data processing: measuring, calibrating, or testing

Calibration or correction system

Position measurement

Reexamination Certificate

active

06708131

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to photolithography processes for manufacturing integrated circuits. More particularly, the invention relates to a method of aligning wafers for successive stepping and scanning stages of a photolithographic process.
BACKGROUND OF THE INVENTION
Photolithography is used to manufacture integrated circuits by exposing a suitably prepared wafer to light passing through a mask. The entire wafer can be exposed at once. Often, however, separate sub-areas of a wafer are successively exposed in a stepping process, or a band of light is directed synchronously across a mask and a region of a wafer in a scanning process. Alignment is critically important when multiple photolithographic processes are used to manufacture an integrated circuit.
Alignment refers to, among other things, the process of registering a mask to a wafer. Many methods of alignment are known. In one method, a wafer is carried on a fixture called a wafer stage. The wafer is indexed to the wafer stage by a notch in its periphery and the wafer stage is supported by a movable carriage. The carriage positions the wafer stage as part of stepping and/or scanning processes.
Mirrors are typically affixed to the wafer stage and as the wafer stage is moved interferometers focused on the mirrors precisely locate the wafer stage to align the wafer stage with the appropriate mask and light source. Typically the wafer stage is rectilinear. Therefore, only two sets of two mirrors, one set parallel to the x-axis and one set parallel to the y-axis, are required to appropriately locate the wafer stage in the x-y plane.
An example of a photolithographic process including stepping and scanning steps is illustrated in
FIGS. 1-3
. In
FIG. 1
, a light source and mask are aligned to expose a first region
1
of a wafer A. In
FIG. 2
, the light source and mask are aligned to expose a second region
2
of wafer A. This constitutes a two-step stepping process. A scanning process then commences. In the first step of the scanning process, a mask is aligned with a third region
3
of wafer A, and a light source traverses the mask exposing region
3
in FIG.
3
.
Alignment of the masks used in the scanning process with the existing stepped regions is critical. This alignment becomes more difficult when the scanning process is completed on a different machine from the stepping process. Moreover, the surfaces of the mirrors used to align the wafer stage are not completely flat, and mirror imperfections will affect alignment when critical dimensions are small. The mirrors, therefore, must be calibrated.
One method to accomplish this inter-machine alignment uses a calibration wafer. According to this method, a calibration wafer is placed in a first machine, and a calibration pattern is printed by the first machine on the calibration wafer. The actual position of the points of the calibration pattern are carefully measured. The calibration pattern measurement data, along with the position of the calibration wafer according to the alignment mirrors of the first machine, is stored in a memory.
The calibration wafer is placed in the second machine in the same orientation as the first machine. A nominally identical calibration pattern is printed by the second machine on the calibration wafer. The actual position of the points of the second calibration pattern are carefully measured. The second calibration pattern measurement data, along with the position of the calibration wafer according to the alignment mirrors of the second machine, is stored in a memory.
The first calibration pattern measurement data, first alignment mirror position, second calibration pattern measurement data and second alignment mirror position are processed to account for, among other things, the disparities of the alignment mirrors. When a production wafer is processed in a first machine, then transferred to a second machine in the same orientation, the processed data from the calibration process is used to adjust the position of the production wafer in the second machine to bring it into true alignment with the regions exposed on the production wafer by the first machine.
When scanning is done in the same linear direction as stepping, once the wafer is placed in the apparatus, its only movement will be along the x and y axes and no rotation to change wafer orientation is necessary. For instance, in
FIG. 10
, a shallow, rectangular first region
1
a
is exposed on a wafer C, followed by a similar second region
2
a
as shown in FIG.
11
. These stepping processes could be followed by one scanning process similar to those shown in FIG.
3
. Sometimes, however, it is advantageous to carry out stepping and scanning processes in different directions with respect to a wafer. For example, as shown in
FIG. 12
, under certain geometries a single pass of the scanner
200
in a direction 90° to the path of the stepper
100
can expose a single region
3
a
covering both regions
1
a
and
2
a.
Many integrated circuit manufacturing centers are not equipped to execute stepping and scanning in different directions. In these manufacturing centers, the wafer must be rotated 90° to accommodate stepping passes orthogonal to scanning passes. This is illustrated in
FIG. 13
, where the wafer C has been rotated 90° to accommodate a region
4
a
scanned in the same linear direction as the stepping processes. When multi-directional stepping and scanning requires a rotation of a wafer, the alignment process described above cannot be used. What is required then, is a method of aligning and manufacturing a rotated production wafer.
SUMMARY OF THE INVENTION
The invention concerns a method for aligning wafers in machines used to manufacture integrated circuits.
In the invention, a first pattern is formed in a calibration wafer in a first orientation in a first machine and a second pattern is formed in the calibration wafer in said first orientation in a second machine. Next, the difference between the first pattern and the second pattern is measured and stored in a memory. The difference is transformed to account for a change in orientation, typically a 90° rotation.
Next, regions in a production wafer in the first orientation are processed in the first machine and the location of the production wafer in the first machine is determined.
The production wafer is then transferred to the second machine in a second orientation, typically at a 90° rotation.
The location of the production wafer in the second machine is determined next, and then adjusted using the transformed difference. Finally, the production wafer is aligned in the second machine using the adjusted location data; and the regions in the production wafer are processed in the second machine.
In one example of the invention, the first machine is a stepper and the second machine is a scanner, each with their own processor and memory. The scanner processor retrieves the coordinates of the cruciform patterns, transforms them, and adjusts the alignment of the production wafer in the scanner using the transformed coordinates.
A 90° change in the orientation of the production wafer is useful when two successive regions of the production wafer are exposed in the stepper in a first direction, the scanning breadth of the scanner exceeds the length of the two successive stepped regions in the first direction, and a single scanning pass in a second direction exposes both successive stepped regions in the production wafer in a single scanning pass.
According to one aspect of the invention, positional differences may be transformed by switching the x-coordinates of the cruciform pattern in the scanner with the y-coordinates of the cruciform pattern in the scanner.


REFERENCES:
patent: 5464715 (1995-11-01), Nishi et al.
patent: 5617340 (1997-04-01), Cresswell et al.
patent: 5740062 (1998-04-01), Berken et al.
patent: 6133986 (2000-10-01), Johnson
patent: 6166509 (2000-12-01), Wyka et al.
patent: 6278957 (2001-08-01), Yasuda et al.
patent: 6285033 (2001-09-01), Matsumoto

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