Wafer alignment system

Details Wafer alignment system Wafer alignment system

1998-11-13

2001-03-06

Font, Peter J. (Department: 2877)

Optics: measuring and testing

By alignment in lateral direction

With registration indicia

C356S399000

Reexamination Certificate

active

06198535

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87113704, filed Aug. 20, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor fabrication process, and more particularly to an alignment system for performing an alignment process on a wafer.
2. Description of Related Art
Among the processes for fabricating a semiconductor device, photolithography is one of the most critical processes since it is directly related to the accuracy of transferring a pattern on to the desired region. Generally, the fabrication of a semiconductor device requires about 10 to 18 masks, that is, performing the same number of photolithography processes.
Before a pattern is transferred onto a desired surface, an alignment process has to be done to ensure the accuracy of patterning. Normally at least two alignment marks are formed on the surface of a wafer to be patterned in order to set the wafer on a correct position. However, various fabricating processes performed on the wafer, such as chemical mechanical polishing, cause damage on the alignment marks, and that further results in a poor alignment and an erroneous pattern transfer.
Referring to
FIG. 1
is a schematic diagram showing a conventional method for aligning a wafer
14
. Referring to
FIG. 1
, the wafer
14
, which has a top surface
13
and a back surface
15
, is placed on a wafer stage
12
, wherein the top surface
13
of the wafer
14
, contains two alignment marks W
1
and W
2
. The wafer stage
12
is located on a fixed base
10
.
The alignment process starts with emitting a guiding ray from an illumination case
16
. The guiding ray is firstly reflected by mirrors
18
and
20
, and then the reflected guiding ray falls onto one of the alignment marks W
1
and W
2
. The guiding ray is then reflected to a reticle
32
through a projection lens
30
by the wafer, wherein the reticle
32
contains marks M
1
and M
2
. Two alignment blocks
34
and
36
are used to confirm the condition of a valid alignment is obtained. The condition of a valid alignment includes that the reflected guiding ray strikes on the marks M
1
and M
2
.
Because most fabrication processes physically change the top surface
13
of the wafer
14
, the alignment marks W
1
and W
2
are deformed and maculed. The physical damages on the alignment marks lead to a poor alignment, poor pattern transfer, or even resulting in abandoning a wafer.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide an alignment system that protects the alignment marks on a wafer from being damaged by other fabrication processes to ensure the quality of alignment and the follow-up processes.
In accordance with the foregoing and other objectives of the present invention, the invention provides an alignment system that aligns a wafer by checking the alignment marks formed on the back surface of the wafer. A number of guiding rays are used to determine the corresponding alignment mark on the back of the wafer to ensure that the wafer is properly aligned.
The alignment system of the invention also includes a wafer stage and a fixed base, wherein the wafer stage and the fixed base contain a number of apertures that allow the guiding rays to pass through and strike on the alignment marks on the wafer.


REFERENCES:
patent: 4652134 (1987-03-01), Pasch et al.
patent: 4952060 (1990-08-01), Ina et al.
patent: 5847190 (1999-02-01), Tanaka
patent: 5929997 (1999-07-01), Lin

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