Wafer alignment marks protected by photoresist

Details Wafer alignment marks protected by photoresist Wafer alignment marks protected by photoresist

2005-06-21

2005-06-21

Crispino, Richard (Department: 1734)

Coating apparatus

Control means responsive to a randomly occurring sensed...

Responsive to attribute, absence or presence of work

C118S500000, C438S975000

Reexamination Certificate

active

06908514

ABSTRACT:
In this invention a coating of unexposed photoresist is used to protect from semiconductor processing the area immediately above a zero layer alignment mark used for a wafer stepper alignment. The entire surface of a wafer is coated with photoresist and all shot sites on the surface of a wafer including those containing the zero layer alignment marks are exposed with circuit patterns. Before the exposed areas of photoresist are removed, a protective coating of unexposed photoresist is applied to the surface of the wafer immediately above the alignment marks but within the boundaries of the shot site. The wafer is processed in the areas outside of the protective coating of photoresist including the shot site containing alignment marks. The area under the protective coating is not processed. This maintains a clear and concise view of the alignment marks. The area beyond the protective coating is processed along with the other shot sites. This produces a homogeneous wafer structure at the peripheral of the shot site containing the alignment marks. Yield in the shot sites surrounding the alignment sites is improved, and alignment errors are reduced as a result of not processing over the alignment marks.

REFERENCES:
patent: 5923915 (1999-07-01), Akimoto et al.
patent: 5926694 (1999-07-01), Chigawa et al.
patent: 6139639 (2000-11-01), Kitamura et al.
patent: 6156625 (2000-12-01), Balamurugan

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