Wafer acceptance testing method and structure of a test key...

Details Wafer acceptance testing method and structure of a test key... Wafer acceptance testing method and structure of a test key...

1998-12-23

2001-02-20

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06191602

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a wafer acceptance testing (WAT) method, including a use of a test key.
2. Description of Related Art
In semiconductor fabrication, a semiconductor device or an integrated circuit (IC) should be continuously tested in every step so as to maintain device quality. Usually, a testing circuit is simultaneously fabricated with a actual device so that quality of the actual device can be judged by a performance of the testing circuit. The quality of the actual device therefore can be well controlled.
A typical method to test a wafer is called a wafer acceptance testing (WAT) method, which can measure defects of the wafer. The WAT method includes providing several test keys distributed in a periphery region of a die, which is desired to be tested. The test keys typically are formed on a scribe line between dies, and are electrically coupled to an external terminal through a metal pad. A module of the test keys is selected and each test key off the selected module is respectively used for a test of different property of the wafer, such as threshold voltage (V
TH
) or saturate current I
DSAT
. A controlled bias is applied to the test keys, and the induced current is read out to detect defects on the wafer.
FIG. 1
is a top view of a wafer, schematically illustrating a typical structure of a wafer. In
FIG. 1
, several dies
102
are formed on a wafer
101
with a matrix distribution. A scribe line
104
is naturally formed between dies
102
. In each of dies
102
, an actual device, including, for example metal-oxide semiconductor (MOS) transistors, capacitors, and interconnects, is formed. In semiconductor fabrication, every process is performed on the whole wafer
101
so that several testing circuits, each of which is similar to the actual device in each of the dies
102
, are also simultaneously formed in the scribe line
104
. The testing circuits are electrically coupled to an external read out circuit through several metal pads
106
. Each pad serves as a testing key
106
for a test of a property desired to be tested. Thus, the test keys
106
are distributed on the wafer
101
and are user to test the wafer. The is a typical WAT method.
Most of device damages or wafer defects in fabrication usually result from plasma processes. Unfortunately, plasma processes are very essential in semiconductor fabrication, such dry etching or doping processes. During the plasma processes, the wafer is bombard by energetic ions and results in a damage. In addition, since the plasma ions carry a lot of charges, it may also cause a damage to the wafer due to statistic charge accumulation. For example, energetic plasma ions can penetrate through a gate to cause a damage to the gate, and further leave their charges inside the gate. Those charges from ions are accumulated by a gate oxide layer, resulting in a degradation of its isolation performance. A device current leakage is therefore induced. All these kinds of damage resulting from plasma processes are called a plasma process induced damage (P2ID).
FIG. 2
is a cross-sectional view of a portion of a substrate, schematically illustrating a structure of a conventional test key. In
FIG. 2
, there is a substrate
200
. A testing structure
202
, such as a transistor or a capacitor, is formed on the substrate
200
. An inter-layer dielectric layer
204
is formed over the substrate
200
is isolate the testing structure
202
. An interconnecting structure
206
is formed on the inter-layer dielectric layer
204
. The interconnecting structure
206
, as usual, includes interconnecting metal layer
208
and inter-metal dielectric layer
210
. A metal pad layer
212
is formed on the interconnecting structure
206
. A passivation layer
214
is on the top. The testing structure
202
is coupled to the interconnecting metal layer
208
through, usually, a contact. Again through a via, the interconnecting metal layer
208
is coupled to the metal pad layer
212
. Desired testing signals can be obtained by reading signals at the metal pad layer
212
.
The structure of the test key shown in
FIG. 2
is simultaneously formed while the actual devices in each die are formed on the substrate
200
at other portion, such as the structure shown in FIG.
1
. The formation of the test key includes several plasma processes. If there is any damage occurring, it can only tell that the actual device may also damage. It is difficult to clearly pin down where the damage is. Device performance defect may result from the damage of the testing structure
202
, the interconnecting structure
206
, or others. Engineers need to spend a lot of time to check every steps to find out which steps may cause damage. This is time consuming and causes a degradation of throughput.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a wafer acceptance testing (WAT) method with an improved test key so as to efficiently find out whether the damage is from a device structure or from an interconnecting structure. Because the damage can be easily find out, the production rate is not degraded. Fabrication cost do not increase.
In accordance with the foregoing and other objectives of the present invention, a wafer acceptance testing (WAT) method with an improved test key is provided. The improved test key structure includes a testing structure on a substrate. An inter-layer dielectric layer covers over the substrate to isolate the testing structure. A grounded metal layer is located on the inter-layer dielectric layer. An interconnecting structure is located on the grounded metal layer. A conductive pad layer and a passivation layer are sequentially located on the interconnecting structure. The testing structure is electrically coupled to the interconnecting structure through, for example, a contact. The interconnecting structure is also electrically coupled to the conductive pad layer. The grounded metal layer is grounded through, for example, a grounded transistor or direct coupling to the substrate. The grounded metal layer is not coupled to the testing structure, the interconnecting structure, or any other structure. In this improved test key structure, the grounded metal layer can protect the testing structure from plasma processes for a formation of the interconnecting structure so that damage from either the testing structure or the interconnecting structure can be easily distinguished.
The WAT method of the invention includes measuring the improved test key to obtain a first testing result, and measuring conventional test key to obtain a second testing result, and analyzing the first testing result and the second testing result. If both the first and the second testing results are abnormal, the test device structure is damaged by plasma process during forming itself. If the first testing result is normal but the second result is abnormal, then the test device structure is damaged by plasma process during forming the interconnecting structure. If both the first and the second testing results are normal, it means that there is not plasma damage.


REFERENCES:
patent: 5966022 (1999-10-01), Budnaitis et al.

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