VSLI latch system and sliver pulse generator with high correlati

Details VSLI latch system and sliver pulse generator with high correlati VSLI latch system and sliver pulse generator with high correlati

1989-06-09

1991-12-10

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 3074821, 3073031, 3072722, 307269, H03K 3284, H01L 2500

Patent

active

050721321

ABSTRACT:
A VSLI circuit includes a plurality of state device circuits on a VLSI chip. Each of the state device circuits includes a latch and is clocked by a pulse generator circuit which produces narrow pulses that are coupled to the clock input of the latch. The narrow pulses have a pulse width substantially equivalent to the propagation delay through the latch of the state device circuits. By taking advantage of the high correlative percentages of devices on portions of the chip, master-slave flip flops can be implemented using only a single latch with a pulse generator.

REFERENCES:
patent: 4701860 (1987-10-01), Mader
patent: 4864161 (1989-09-01), Norman et al.
patent: 4883980 (1989-11-01), Morimoto et al.

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