Voter subsystem for a fault tolerant multiple node processing sy

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364734, G06F 1108

Patent

active

049724150

ABSTRACT:
A voter subsystem for a multiple node fault tolerant system having an upper medial value sorter for sorting a plurality of received values to generate an upper medial value and a lower medial value sorter for sorting the same plurality of received values to generate a lower medial value. An averaging circuit adds the upper and lower medial values then divides by two to generate a voted value. A deviance checker checks each of the plurality of received values against the voted value to generate a deviance error for each received value which differed from the voted value by a predetermied amount. A loader loads the plurality of received values into the upper and lower medial value sorters and the deviance checker bit-by-bit, starting from the most significant bit positions through the least significant bit positions. The upper and lower medial value sorters and deviance checker process the received values on-the-fly in the order they are received.

REFERENCES:
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patent: 3667057 (1972-05-01), Pfersch, Jr. et al.
patent: 3805235 (1974-04-01), Foster et al.
patent: 4143353 (1979-03-01), Schaible
patent: 4375683 (1983-03-01), Wensley

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