Voltage translator, particularly of the CMOS type

Details Voltage translator, particularly of the CMOS type Voltage translator, particularly of the CMOS type

2001-03-30

2003-02-11

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C326S068000

Reexamination Certificate

active

06518816

ABSTRACT:

TECHNICAL FIELD
This invention relates to a voltage translator, particularly of the CMOS type.
Specifically, the invention relates to a CMOS voltage translator that has a differential cell circuit portion connected between first and second supply voltage references, and first and second transistor pairs connected together in series between the supply voltage references.
BACKGROUND OF THE INVENTION
As is known, voltage translators are used in several applications, especially in integrated circuits, for the purpose of bringing a supply voltage of relatively low level (typically 3.3 to 5 V) to conveniently higher and/or lower values dependent on the requirements of various circuitry connected to the voltage supply.
A voltage translator is applied to a MOS transistor, where a high voltage may impair its reliability by causing the gate oxide to break down.
A prior solution, wherein an upper limit is placed on the value of the high-voltage supply, is shown generally in FIG.
1
A and in more detail in
FIG. 1B. A
conventional voltage translator
1
, being supplied a high-voltage reference VDDHIGH, is input a reference voltage VREF obtained from a voltage divider
2
, with the latter being supplied with the high-voltage reference VDDHIGH and an input signal VIN.
It should be noted that the high-voltage reference VDDHIGH lies, for example, above the highest voltage value that can be applied to a MOS transistor.
In particular, the high-voltage reference VDDHIGH is applied to a first pair of P-type MOS transistors, MP
1
and MP
2
, which are cross-connected together such that their gate and drain terminals are respectively connected to the source terminals of a second pair of P-type MOS transistors, MP
3
and MP
4
. The gate terminals of the second transistor pair receive a reference voltage VREF from the voltage divider
2
.
Also, the drain terminals of the second transistor pair MP
3
, MP
4
are respectively connected to the source terminals of a pair of N-type MOS transistors, MN
1
and MN
2
, whose gate terminals are driven respectively by the input signal VIN, presented at an input terminal IN of the voltage translator
1
, and its inverse, i.e., a low-voltage reference VDDLOW obtained from an inverter INV which is connected between the input terminal IN and the gate terminal of the transistor MN
2
. The voltage translator
1
also has an output terminal OUT coinciding with the drain terminal of the transistor MP
3
.
Furthermore, the bulk terminals of the transistors MP
1
, MP
2
, MP
3
and MP
4
are connected to the high-voltage reference VDDHIGH.
As shown in
FIG. 1B
, the voltage divider
2
comprises first and second P-type MOS transistors, MP
5
and MP
6
, in a diode configuration, which transistors are connected, in series with each other, between the high-voltage reference VDDHIGH and a ground reference GND.
In the instance of the transistors MP
5
and MP
6
being selected identical with each other, a value of the reference voltage VREF is obtained which is half that of the high voltage VDDHIGH, namely:
VREF=VDDHGH/2.
The operation of the voltage translator
1
under different operational conditions will now be reviewed.
In the event of the value of an input signal VIN applied to the input terminal IN being equal to that of the low-voltage reference VDDLOW, the drain terminals of the transistors MP
1
and MP
3
would be at VDDHIGH, and the drain terminals of the transistors MP
4
and MP
2
would be at GND and VDDHIGH+Vth(MP
4
), respectively, where Vth(MP
4
) is the threshold voltage value of the transistor MP
4
.
It should be noted that the terminals of all P-type MOS transistors have a voltage drop of VDDHIGH+Vth(PMOS), where Vth(PMOS) is the threshold voltage value of a PMOS transistor. This value is usually suitable for supply to the transistors under consideration. Otherwise, additional stages of the cascode type, that is additional pairs of PMOS transistors in the same configuration as transistors MP
3
and MP
4
, would have to be provided.
It should also be noted that the drain terminal of transistor MN
1
would be at VDDHIGH, this value being an acceptable one only because NMOS transistors of the drift type are used instead of standard NMOS transistors.
When the input signal VIN at the input terminal IN is changed from a value equal to GND to a value equal to the low-voltage supply reference VDDLOW, the drain terminal of the transistor MN
1
is brought down to GND, and the source terminal of the transistor MP
3
up to the value of VREF+Vth(MP
3
), where Vth(MP
3
) is the threshold voltage value of the transistor MP
3
; as the voltage across the gate and source terminals of the transistor MP
3
drops below the threshold voltage Vth(MP
3
) of the transistor MP
3
, the latter is turned off.
Likewise, when the voltage value, equal to VDDHIGH−VREF+Vth(MP
3
), across the gate and source terminals of the transistor MP
2
rises above the value of the threshold voltage of the latter, the transistor MP
2
is turned on and the transistor MP
1
turned off; the value of the voltage at the output terminal OUT of the voltage translator
1
rises to the high voltage VDDHIGH.
In this condition of operation, the greatest drop in voltage across the terminals of the PMOS transistors comprising the voltage translator
1
would still be VDDHIGH+Vth(PMOS).
Thus, a prerequisite for the voltage translator
1
to operate correctly, is that all the PMOS transistors contained in it should be capable of withstanding that voltage maximum on their gate oxides.
Another prior solution is shown generally in FIG.
2
A and in more detail in FIG.
2
B. Similar elements carry the same reference numerals and will not be described further.
In particular, it can be seen that an intermediate voltage translator
3
has been connected between the voltage translator
1
and the voltage divider
2
, which intermediate translator
3
is supplied a high reference voltage VREFHIGH generated from a voltage source
3
for low-impedance loads, itself connected to the high-voltage reference VDDHIGH.
The intermediate translator
3
is input the reference voltage VREF and the input signal VIN, and supplies first and second intermediate reference voltages, VREF and VREF
2
, to the translator
1
. The voltage translator
1
is further input the high reference voltage VREFHIGH.
In particular, the intermediate translator
3
is configured same as the translator
1
, but is supplied the high reference voltage VREFHIGH.
In particular, this high reference voltage VREFHIGH is supplied to a first pair of P-type MOS transistors, M
14
and M
15
, which are cross-connected together such that their gate and drain terminals are respectively connected to the source terminals of a second pair of P-type MOS transistors, M
12
and M
13
. The gate terminals of the second transistor pair receive a reference voltage VREF from the voltage divider
2
.
The drain terminals of the second transistor pair M
12
, M
13
are respectively connected to the source terminals of a further pair of N-type MOS transistors, M
11
and M
10
, having their gate terminals driven respectively by the input signal VIN, presented at an input terminal IN of the voltage translator
1
, and its inverse, i.e., a low-voltage reference VDDLOW obtained from a further inverter INV being connected between the input terminal IN and the gate terminal of the transistor MN
2
.
The intermediate translator
3
has a first output terminal OUT
1
coinciding with the drain terminal of the transistor M
14
, and has a second output terminal OUT
2
coinciding with the drain terminal of the transistor M
15
. In particular, the first output terminal OUT
1
is to supply said first intermediate reference voltage VREF
1
to the gate terminal of the transistor MP
4
in the voltage translator
1
, and the second output terminal OUT
2
is to supply said second intermediate reference voltage VREF
2
to the gate terminal of the transistor MP
3
in the voltage translator
1
.
Lastly, yet another pair of PMOS transistors, MP
9
and MP
10
, are connected between

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