Voltage translator for interfacing TTL and CMOS circuits

Details Voltage translator for interfacing TTL and CMOS circuits Voltage translator for interfacing TTL and CMOS circuits

1977-06-22

1978-12-05

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307208, 307251, 307297, 307315, 307DIG1, H03K 1760, H03K 102, H03K 114, H03K 1908

Patent

active

041287754

ABSTRACT:
The invention described herein is an interface circuit which effectively allows TTL output voltages to fall within the range of CMOS input thresholds. The interface circuit contains bipolar and FET devices connected to generate an input voltage threshold which is equal to two base-emitter voltage drops. The interface circuit also includes a switching circuit portion which comprises one P-channel MOS transistor connected to one N-channel MOS transistor.

REFERENCES:
patent: 3622812 (1971-11-01), Crawford
patent: 3676700 (1972-07-01), Buchanan
patent: 3755690 (1973-08-01), Smith
patent: 3898477 (1975-08-01), Buchanan
patent: 3900746 (1975-08-01), Kraft et al.
patent: 3906254 (1975-09-01), Lane et al.
patent: 3916430 (1975-10-01), Heuner et al.
patent: 4023050 (1977-05-01), Fox et al.
patent: 4031409 (1977-06-01), Shimada et al.
patent: 4032795 (1977-06-01), Hale
Blaser et al., "Level Converting Circuit", IBM Tech. Discl. Bull.; vol. 18, No. 11, pp. 3722; 4/1976.
Askin et al., "Level Converting Circuit", IBM Tech. Discl. Bull.; vol. 18, No. 11, pp. 3723, 4/1976.
Freeman, "Level Shifting Circuit", IBM Tech. Discl. Bull.; vol. 18, No. 5, pp. 1450, 10/1975.

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