Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1998-09-22
2001-05-15
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C326S081000
Reexamination Certificate
active
06232818
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuits. Specifically, the present invention relates to a voltage level converter and a semiconductor integrated circuit adapting the same, and more specifically to improvement of an interface circuit used between circuits having different driving power sources and for converting a signal level between these circuits.
Integrated circuit geometries continue to decrease in size, providing more devices per unit area on a fabricated wafer. Currently, some devices are fabricated with feature dimensions as small as 0.18 &mgr;m. For example, spacing between conductive lines or traces on a patterned wafer may be separated by 0.18 &mgr;m leaving recesses or gaps of a comparable size. The reduction in feature dimensions has necessitated reducing the operating voltage of integrated circuits to avoid latch-up and other operational defects. Currently, CMOS circuitry operates at 3.3 volts or 2.5 volts, and there are efforts to reduce the operating voltages further, e.g., in the range between 2.5 and 1.8 volts.
As a result of the continued effort to reduce the operating voltage of integrated circuits, many of the present day circuits operate at differing voltage levels, requiring an interface, typically referred to as a voltage translator. In this fashion, introduction of integrated circuits into the current market is facilitated by allowing the same to operate with integrated circuits having different operating voltages which are typically higher. There has been many prior art attempts at fabricating voltage translators.
Referring to
FIG. 1
, an example of a prior art voltage translator
10
includes a first stage inverter
12
connected to a second stage inverter
14
via a pass-gate transistor
15
. The input
16
of the second stage inverter
14
is connected to the drain
18
of the pass-gate transistor
15
, and the output
20
of the first stage inverter
12
is connected to the source
22
thereof. The gate
15
a
of the pass-gate transistor
15
is connected to a first voltage level referred to as V
LOW
. Both the first and second stage inverters
12
and
14
include a p-channel transistor
24
and
26
, respectively, and an n-channel transistor
28
and
30
, respectively, each of which has a gate, a source and a drain. The gate
24
a
of the p-channel transistor
24
is connected to the gate
28
a
of the n-channel transistor
28
, defining the signal input
17
of the voltage translator
10
. The source
28
b
of the n-channel transistor
28
is connected to the drain
24
c
of the p-channel transistor
24
, defining the output
20
of the first stage inverter
12
. The drain
28
c
of the n-channel transistor
28
is connected to ground. The source
24
b
of the p-channel transistor
24
is connected to the low voltage V
LOW
. The gate
26
a
of the p-channel transistor
26
is connected to the gate
30
a
of the n-channel transistor
30
, defining the input
16
of the second stage inverter
14
. The source
30
b
of the n-channel transistor
30
is connected to the drain
26
c
of the p-channel transistor
26
, defining the signal output
19
of the voltage translator
10
. The drain
30
c
of the n-channel transistor
30
is connected to ground. The source
26
b
of the p-channel transistor
26
is connected to a second voltage level that is higher than V
LOW
, referred to as V
HIGH
. A pull-up transistor
32
is connected to the second stage inverter
14
so that the gate
32
a
thereof is connected to the signal output
19
, and the drain
32
c
is connected to the gates
26
a
and
30
a.
When transitioning from a high to a low signal at the signal input
17
, the p-channel FET
24
is activated while the n-channel FET
28
is deactivated. This presents V
LOW
at output
20
. The voltage at the output
20
passes through the pass-gate transistor
15
and is present at the input
16
, minus the threshold voltage drop of the pass-gate transistor
15
. This voltage, referred to as a switching voltage, activates n-channel FET
30
, but is typically insufficient to completely deactivate p-channel FET
26
. The signal output
19
is at ground which activates pull-up transistor
32
. This allows V
HIGH
to be present at the input
16
, effectively deactivating p-channel FET
26
. In this fashion, the pass-gate transistor
15
essentially functions to isolate the V
HIGH
voltage source from the V
LOW
voltage source by ensuring that output
20
does not rise above V
LOW
, minus the threshold voltage of pass-gate transistor
15
. Otherwise, latch-up would occur.
When transitioning from a low to a high signal at the signal input
17
, p-channel FET
24
is deactivated while n-channel FET
28
is activated. This presents ground at output
20
, which is sensed at input
16
via pass-gate transistor
15
. This deactivates n-channel FET
30
and activates p-channel FET
26
. The signal output is V
HIGH
which deactivates pull-up transistor
32
. Typically the high voltage level at the signal input
17
is equal to V
LOW
. In this manner, a high voltage level at the signal input
17
is translated into a higher voltage level at the signal output
19
.
U.S. Pat. No. 5,276,366 to Quigley et al. discloses another voltage level translator circuit for interfacing circuitry operating at different voltages. An inverting digital voltage level translator circuit has an input and an output. The input is coupled to a transmission gate, an inverter, and a gate of an n-channel FET. The transmission gate is enabled by the inverter when the input is at a zero logic level. An output of the transmission gate is coupled to both a gate of a p-channel FET and an output of a pull-up circuit. A zero logic level at the input enables p-channel FET through transmission gate and disables the n-channel FET, generating a one logic level at the output. A one logic level at the input enables the n-channel FET transitioning the output to a zero logic level. Output to a control input of pull-up circuit and a zero logic level enables the pull-up circuit to disable the p-channel FET.
U.S. Pat. No. 5,574,389 to Chu discloses interfacing components for VLSI chips designed to migrate from 5 volt designs to lower voltage designs. The interfacing components have different power supplies and pass voltages at the output node of a CMOS buffer circuit to the isolation well of a p-channel FET in a buffer circuit when the voltage at the output node is greater than the voltage at the buffer voltage supply node. This prevents forward biasing the PN junction in the isolation well of the p-channel FET. The circuits also provide the proper voltage level to the gate of the p-channel FET.
U.S. Pat. No. 5,680,064 to Masaki et al. discloses a first level converter with an input transistor circuit and an output transistor circuit. The input transistor circuit is supplied with power from a first power source and outputs a complementary signal on the basis of an input signal. The output transistor circuit is supplied with power from a second power source and amplifies and outputs the complementary signal. A second level converter is provided with a pulse generating circuit and a signal output circuit. The pulse generating circuit is supplied with power from the first driving power source and generates a one-shot pulse signal. The signal output circuit is supplied with power from the second power source and latches the one-shot pulse signal and outputs the signal. The semiconductor integrated circuit is provided with a first circuit system, a level conversion circuit and a second circuit system. The first circuit system is driven by being supplied with power from the first driving power source. The level conversion circuit is supplied with power from the first driving power source and converts an output signal of the first circuit system into an input signal of the second circuit system. The second circuit system drives a signal with the level converted by being supplied with power from the second driving power source. Further, in the semiconductor integrated circuit,
Townsend & Townsend
Xilinx , Inc.
Zweizig Jeffrey
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