Voltage-tolerant electrostatic discharge protection device for i

Details Voltage-tolerant electrostatic discharge protection device for i Voltage-tolerant electrostatic discharge protection device for i

1996-03-21

1998-02-17

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 56, 361118, H02H 322

Patent

active

057197377

ABSTRACT:
A method and an apparatus for protecting an integrated circuit from electrostatic discharge. In one embodiment, a voltage reduction circuit coupled to a termination circuit are coupled between a power supply and ground. The disclosed voltage reduction circuit utilizes a cantilevered diode string coupled to a clad network. Coupled to the voltage reduction circuit and the termination circuit is a voltage divider circuit which is coupled between the power supply and ground. The voltage supplied to the voltage reduction circuit and the termination circuit is a lower voltage than the steady state power supply voltage and is a tolerable voltage for gate oxides of a low voltage process. In another embodiment of the present invention, a voltage reduction circuit utilizing a stacked gate scheme is coupled between the power supply and ground. A voltage divider circuit is used in this embodiment to provide a bias voltage. The bias voltage is supplied to the voltage reduction circuit and a control circuit. The disclosed control circuit generates an output signal turning on the voltage reduction circuit during an ESD pulse and subsequently turning off the voltage reduction circuit after a period of time has elapsed after the ESD pulse. Accordingly, ESD protection is provided to the integrated circuit power supply of a low voltage process with minimal leakage current.

REFERENCES:
patent: 3573550 (1971-04-01), Baker, Jr.
patent: 3943427 (1976-03-01), Tolstov et al.
patent: 4585905 (1986-04-01), Brown
patent: 5311391 (1994-05-01), Dungan et al.
patent: 5546016 (1996-08-01), Allen
"Mixed-Voltage Interface ESD Protection Circuits For Advanced Microprocessors In Shallow Trench and LOCOS Isolation CMOS Technologies," IEEE, Voldman et al., pp. 10.3.1-4, 1994.

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