Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Converting input voltage to output current or vice versa
Reexamination Certificate
2003-09-25
2004-12-07
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Converting input voltage to output current or vice versa
C363S073000
Reexamination Certificate
active
06828832
ABSTRACT:
BACKGROUND OF INVENTION
Field of the Invention
The present invention relates to analog converters and more particularly to an improved voltage to current converter circuit using a variable bias voltage in the half cascode current mirror in the output stage that is well adapted to phase locked loop (PLL) applications.
To date, the digital IC chips that are packaged on a printed circuit board are generally clocked by a so-called main or system clock which is distributed on the whole board. Even these chips are identical, because they may have different specifications depending they are in the best, nominal or worst case conditions, the clock signals that are derived from the main clock may arrive at different times, so that, for instance, the sampling operations are performed with more or less time shift. This is the role of Phase Locked Loop (PLL) circuits to realign the clock signals in said digital chips for signal synchronization outside the chips. In particular, analog hardware macro PLLs, such as standard PLLs, video/audio PLLs, and the like are widely used inside digital circuits such as microprocessors, DSPs, MPEG 2 decoders, and the like in order to minimize the clock skew at the board level. Unfortunately, PLLs are not perfect circuits and they may induce internal jitter that often becomes the main contributor to clock skew. Therefore, the lower the jitter, the higher the circuit speed and global performance.
Conventional PLLs are generally comprised of a voltage to current (V
2
I) converter circuit followed by a current controlled oscillator (CCO) circuit.
FIG. 1
a
schematically shows the block diagram architecture of such a conventional V
2
I converter circuit. Now turning to
FIG. 1
a
, the V
2
I converter circuit referenced
10
is basically comprised of three stages referenced
11
,
12
and
13
. The first stage
11
is formed by two differential amplifiers
14
and
15
having their inputs adequately connected in parallel at input terminals
16
and
17
respectively. Single-ended input voltage signals V
FILTP
and V
FILTN
supplied by filters in a preceding stage (not shown) are applied to said input terminals
16
and
17
respectively, to create a differential input voltage Vin therebetween. Likewise, the outputs of differential amplifiers
14
and
15
are connected in parallel at nodes
18
and
19
respectively. The second stage
12
consists of a transconductor formed by three current sources
20
,
21
and
22
biased between a positive voltage A
VDD
and the ground G
nd
to generate currents
2
I,
2
I and I respectively. Current source
20
is connected to node
18
and current sources
21
and
22
are connected to node
19
. Because V
2
I converter circuits are generally constructed by analog blocks implementing CMOSFET transistors, these current sources typically feed two NMOS transistors TN
1
and TN
2
mounted in a current mirror mode (typically in a cascode configuration) with a common gate connection at node
23
(same potential as node
18
). Finally, a half cascode current mirror forms the third stage
13
, also referred to hereinbelow as the output stage. It consists of transistors TN
3
and TN
4
. Transistor TN
3
will be referred to hereinbelow as the output cascode transistor. The drain of NMOS transistor TN
3
and the gate of transistor TN
4
are tied to node
24
(same potential as node
19
) which also plays the role of the output terminal for the whole V
2
I converter circuit
10
. The gate of TN
3
receives a constant voltage V, which is around 0.7 V, supplied by a biasing circuit consisting of a current source generating a current I
b
and a resistor R (or a transistor). The current I
c
which flows into transistors TN
3
and TN
4
creates an output voltage V
IIO
at output terminal
24
. Output voltage V
IIO
is applied to the input of the other half cascode current mirror placed in the CCO (not shown) as standard. A similar circuit combination (V
2
I and CCO) is described in the article “Fully Integrated CMOS Phase Locked Loop with 15 to 240 MHz Locking Range and +/−50 Jitter” authored by Ilya I. Novof & al, and published in the IEEE Journal of Solid State Circuits, vol. 30, N
o
11, November 1995, pages 1259-1266.
In reality, the voltage to current converter properly said only consists of stages
11
and
12
, in order to inject a current I
c
, function of the differential input voltage Vin in the half cascode current mirror of the third stage
13
.
FIG. 1
b
shows the relation between the current I
c
and the differential input voltage Vin equal to V
FILTP
−V
FILTN
. As apparent in
FIG. 1
b
, I
c
=I when V
FILTP
−V
FILTN
=0.
FIG. 2
shows a typical detailed hardware implementation referenced
10
″ of the V
2
I converter circuit
10
of
FIG. 1
still in a CMOSFET technology. Like reference (with prime) numerals are used through the several drawings to designate identical (corresponding) parts. Now turning to
FIG. 2
, the two differential amplifiers
14
and
15
of the first stage
11
have an identical construction and are formed by two pairs of three NMOS transistors, TN
5
, TN
6
, TN
7
and TN
8
, TN
9
, TN
10
respectively that are connected as standard. As apparent in
FIG. 2
, in the second stage
12
, each current source is formed by a pair of PMOS transistors TP
1
/TP
2
, TP
3
/TP
4
and TP
5
/TP
6
to generate the
2
I,
2
I and I currents respectively. On the other hand, two NMOS transistors TN
11
and TN
12
have been added to transistors TN
1
and TN
2
to complete a cascode current mirror for proper operation thereof. Finally, the third stage
13
remains unchanged with respect to FIG.
1
. Reference voltage V
0
and V
1
are applied to the gate of transistors TN
11
/TN
12
and TN
7
/TN
10
respectively. Supply voltage A
VDD
and biasing voltages V
BP0
and V
BP1
are adequately connected to these transistors as shown in FIG.
2
.
The CMOSFET transistors of the V
2
I converter circuit
10
′ (and the CCO as well) usually operate in the saturation mode. The jitter that is observed at the CCO circuit output increases if some transistors leave the saturation mode. Unfortunately, in the third stage
13
, NMOS transistors TN
3
and TN
4
cannot be fully saturated at the same time, i.e. the well-known relation Vds>Vgs−Vt which describes the saturation state for a MOS transistor cannot be simultaneously met. This results of their serial connection to realize a cascode current mirror circuit located at the V
2
I converter circuit
10
′ output which is fed by the current supplied by the second stage and of the fact that NMOS cascode output transistor TN
3
is biased by a constant voltage V
BN0
. Depending upon the current I
c
value which varies between approximately 0 and approximately 2I, either transistor TN
3
or TN
4
goes out of the full saturation, and therefore is no longer noise immune, finally causing a jitter increase which is detrimental to the overall CCO performance.
The saturation voltage margins of transistors TN
3
and TN
4
are a function of I
c
and V
BN0
, but unfortunately, for a given value of the bias voltage V
BN0
, the two functions are not constant, but rather vary in opposite directions. As a matter of fact, the saturation voltage margin of transistor TN
3
is a rising function when I
c
increases unlike saturation voltage margin of transistor TN
4
which is a falling function. Consequently, the optimization of saturation conditions cannot be met on a wide current I
c
range.
FIG. 3
shows a plot of Montecarlo simulations describing the saturation voltage margins with the V
2
I converter circuit
10
′ performed on 100 cases with a biasing voltage V
BN0
equal to 0.7 V. This voltage value is easily obtained by injecting a 20 &mgr;A current in a diode-connected FET transistor. A current I
c
is simulated and it is assumed to include commutation noise. To that end, this current is 10% modulated at a frequency of 143 MHz (period T=7 ns). As apparent in
FIG. 3
, the saturation voltage margins (in mV) of respective transist
Cioffi James J.
Nguyen Minh
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