Voltage switching circuit

Details Voltage switching circuit Voltage switching circuit

2001-10-26

2002-12-31

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

C327S373000

Reexamination Certificate

active

06501323

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-330973, filed Oct. 30, 2000; and No. 2001-308693, filed Oct. 4, 2001, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage switching circuit and more specifically to a voltage switching circuit for use in non-volatile semiconductor devices that utilize a voltage higher than supply voltages for NAND cells, NOR cells, DINOR cells, or AND cells.
2. Description of the Related Art
Devices that use a boosted voltage higher than a supply voltage, typically non-volatile semiconductor devices, need a circuit that allows one interconnect line to charge selectively to ground voltage, a supply voltage Vcc, or a high voltage more than the supply voltage. An example of a conventional voltage switching circuit having such a function is illustrated in FIG.
1
.
The voltage switching circuit of
FIG. 1
comprises a first circuit consisting of a P-channel transistor Q
P1
and an N-channel transistor Q
N1
which are enhancement-mode devices and connected together at a node N
1
, a second circuit, or a high voltage output circuit, connected to an output node N
2
, and a third circuit consisting of an N-channel transistor Q
D3
which is a depletion-mode device having a thick gate insulating film and connected between the nodes N
1
and N
2
. The thick gate insulating film of the transistor Q
D3
is intended to withstand a high voltage output from the high-voltage output circuit
20
to the drain side of Q
D3
.
In the first circuit, the transistor Q
P1
has its source and substrate connected together to the supply voltage Vcc, its gate connected to receive a signal Sig
1
, and its drain connected to the node N
1
, while the transistor Q
N1
has its source connected to ground (0 V), its gate connected to receive a signal Sig
2
, and its drain connected to the node N
1
.
In the second circuit, or the high voltage output circuit
20
, a signal Sig
3
is input and a high voltage V
PP
is output to the node N
2
. The high voltage V
PP
is used as a program voltage for a non-volatile semiconductor device.
In the third circuit, the transistor Q
D3
has its source connected to the node N
1
, its gate connected to receive a signal Sig
6
, and its drain connected to the node N
2
. The third circuit consisting of Q
D3
is closely related to the main part of the voltage switching circuit of the present invention as will be shown later and is therefore particularly indicated enclosed by broken line
10
.
The operation of the voltage switching circuit shown in
FIG. 1
will be described next. The signals Sig
1
, Sig
2
, Sig
3
and Sig
6
are set to go from Vcc (high level) to 0 volts (low level) or vice versa. In some cases, the signal Sig
6
can take a voltage # higher than 0 volts as its high level.
In the first circuit, when both the signals Sig
1
and Sig
2
go high, Q
P1
turns off and Q
N1
turns on, causing the node N
1
to go to 0 volts. On the other hand, when the signals Sig
1
and Sig
2
go low, Q
P1
turns on and Q
N1
turns off, so that the node N
1
goes to Vcc. When the signal Sig
1
goes high and the signal Sig
2
goes low, both Q
P1
and Q
N1
turn off, so that the node N
1
is placed in the floating (high impedance) state. In this manner, 0 volts, Vcc or high-impedance state can be output to the node N
1
through the use of the signals Sig
1
and Sig
2
.
In the second circuit, when the input signal Sig
3
to the high-voltage output circuit
20
is raised to the high level, a high voltage V
PP
is output to the node N
2
. On the other hand, when the signal Sig
3
goes low, the node N
2
is placed in the high-impedance state.
In the third circuit, when the signal Sig
6
goes high, the transistor Q
D3
turns on, so that the path between the nodes N
1
and N
2
is rendered conductive. When the signal Sig
6
goes low, the transistor Q
D3
goes into the nonconductive state, causing the path between the nodes N
1
and N
2
to be cutoff.
Although the operation of each of the first, second and third circuits has been described separately, the correspondence between the levels of the signals Sig
1
, Sig
2
, Sig
3
and Sig
6
and the output voltages of the conventional voltage switching circuit can be represented as follows:
(a) [Vcc, 0V, 0V, #]=>[no output voltage (high-impedance state)]
(b) [Vcc, Vcc, 0V, #]=>[output voltage=0V]
(c) [0V, 0V, 0V, Vcc]=>[output voltage=Vcc]
(d) [0V, 0V, Vcc, 0V]=>[output voltage=V
PP
]
The voltages within [ ] correspond to Sig
1
, Sig
2
, Sig
3
, and Sig
6
, respectively. In the case of (a) and (b), the voltage level # of Sig
6
has only to be higher than 0 volts.
The feature of the voltage switching circuit shown in
FIG. 1
is the provision of the depletion transistor Q
D3
between the output node N
2
to which the high voltage V
PP
is output and the node N
1
to which voltages of Vcc or less are applied. The implementation of cutoff of the path between the nodes N
1
and N
2
through a single transistor allows the circuit pattern area to be reduced.
In
FIGS. 2A and 2B
there is illustrated the operation of the third circuit
10
. As described previously, in order for the voltage switching circuit to output desired voltages, the transistor Q
D3
is required to display such characteristics as indicated by dotted arrows in
FIGS. 2A and 2B
.
Assume here that the gate voltage of Q
D3
is Vg, the source voltage is Vs, and the drain voltage is Vd. Then, Vg corresponds to the voltage of Sig
6
, Vs to the voltage at the node N
1
, and Vd to the voltage at the node N
2
. As shown in
FIG. 2A
, therefore, the transistor Q
D3
should be rendered nonconductive when [Vg, Vs, Vd]=[0V, Vcc, V
PP
] and, as shown in
FIG. 2B
, the source supply voltage Vcc should be transferred to the drain when [Vg, Vs]=[Vcc, Vcc].
When the cutoff characteristic of Q
D3
shown in
FIG. 2A
is obtained, leakage current associated with high voltage V
PP
will flow from the drain to the source, resulting in the V
PP
level dropping. When the conductive characteristic of Q
D3
shown in
FIG. 2B
is not obtained, the output voltage Vcc of the voltage switching circuit is lowered.
In general, when Vcc is high, (Vg−Vs)=−Vcc in
FIG. 2A
increases in the negative direction and as a result the margin for the cutoff characteristic of Q
D3
increases, allowing the absolute value of the threshold voltage (a negative value) of the transistor Q
D3
to be increased. For this reason, the Vcc transfer state (on state) shown in
FIG. 2B
can be achieved with a sufficient margin. However, in order to achieve the cutoff characteristic of
FIG. 2A
with Vcc decreased, it is required to decrease the absolute value of the threshold voltage of Q
D3
. Thus, the margin for the threshold voltage of Q
D3
for the Vcc transfer state decreases with decreasing Vcc.
That is, in
FIG. 2A
, Vg−Vs (0V−Vcc=−Vcc) required to turn off the depletion transistor Q
D3
approaches 0 volts with decreasing Vcc, which requires the threshold voltage of Q
D3
to be set close to 0 volts to cut off the third circuit
10
. Therefore, the margin for the Vcc transfer state decreases.
In recent years, with decreasing power dissipation of semiconductor integrated circuits, the supply voltage used has been increasingly lowered, which involves difficulties in satisfying the characteristics of the n-channel depletion transistor Q
D3
shown in
FIGS. 2A and 2B
. For this reason, such circuits as shown in
FIGS. 3 and 4
have come into use which involve many components instead of using a depletion transistor.
The circuit of
FIG. 3
is a voltage switching circuit which uses a third circuit
10
a
that is composed of an n-cha

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