Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with other solid-state active device in integrated...
Reexamination Certificate
1997-10-17
2003-10-21
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with other solid-state active device in integrated...
C257S142000, C257S147000, C257S149000, C257S329000
Reexamination Certificate
active
06635906
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to semiconductor high voltage devices, and specifically to semiconductor high voltage devices with voltage sustaining layer containing floating regions.
BACKGROUND OF THE INVENTION
It is well-known that in many semiconductor devices, such as VDMOST and SIT, a high sustaining voltage always accompanies a high specific on-resistance. This is due to the fact that, for a high sustaining voltage, thickness of a voltage sustaining layer should be large and doping concentration of the voltage sustaining layer should be low, so as the peak field does not exceed the critical field for breakdown −E
C
, which is normally expressed by E
C
=8.2×10
5
×V
B
−0.2
V/cm for silicon, where V
B
is the breakdown voltage of the voltage sustaining layer.
In a uniformly doped n-type voltage sustaing layer between a p
+
-region and an n
+
-region, in order to obtain a minimum specific on-resistance at a given breakdown voltage, a doping concentration N
D
and a thickness W of the voltage sustaining layer are optimized such that a maximum field is at p
+
-n-junction and its value is equal to E
C
, a minimum field is at n
+
-n-junction and equal to E
C
/3. For silicon device,
N
D
=1.9×10
18
×V
B
−1.4
cm
−3
(1)
W
=1.8×10
−2
×V
B
1.2
&mgr;m (2)
(see, e.g., P. Rossel, Microelectron. Reliab., vol. 24, No. 2, pp. 339-366, 1984)
In a VDMOST shown in
FIG. 1A
, a field profile in the voltage sustaining layer at V
B
is shown in
FIG. 1B
, where a slope of the field versus distance is qN
D
/&egr;s, &egr;s is the permittivity of the semiconductor and q is the electron charge. The change of the field through the n-region is qN
D
W/&egr;s=2E
C
/3. The relation between R
on
and V
B
of a n-type voltage sustaining layer is then expressed by
R
on
=W/q &mgr;
n
N
D
=0.83×10
−8
×V
B
2.5
&OHgr;.cm
2
(3)
where &mgr;
n
is the mobility of the electron and &mgr;
n
=710×V
B
0.1
cm/V.sec is used for silicon.
In order to get even lower R
on
at a given V
B
, some research have been done to optimize the doping profile instead of using a uniform doping, see: [1] C. Hu, IEEE Trans. Electron Devices, vol. ED-2, No. 3, p243 (1979); [2] V. A. K. Temple et al., IEEE Trans. Electron Devices, vol. ED-27, No. 2, p243 (1980); [3] X. B. Chen, C. Hu, IEEE Trans. Electron Devices, vol. ED-27, No. 6, p985-987 (1982). However, the results show no significant improvement.
SUMMARY OF THE INVENTION
The purpose of this invention is to provide a semiconductor high voltage device having a new voltage sustaining layer with better relationship between R
on
and V
B
. To achieve the above purpose, a semiconductor high voltage device is provided, which comprises a substrate of a first conductivity type, at least one region of a second conductivity type, and a voltage sustaining layer of the first conductivity type having a plurality of discrete floating (embedded) islands of a second conductivity between said substrate and said region of second conductivity type.
According to this invention, an n(or p) type voltage sustaining layer is divided by (n−1) planes into n sub-layers with equal thickness, p(or n) type discrete floating islands are introduced with their geometrical centers on such planes. The average dose N
T
of the floating islands in each plane is about 2e
s
E
C
/3q. For silicon,
N
T
=2&egr;
S
E
C
/3
q
=3.53. 10
12
V
B
−0.2
cm
−2
(4)
With such a floating island, the field is reduced by an amount about 2E
C
/3 from a maximum value E
C
at a side of the floating island to a minimum value E
C
/3 at another side of the floating island so far as the floating island is fully depleted. Each sub-layer is designed to sustain a voltage of V
B1
=V
B
, and to have a thickness and a doping concentration which are almost the same as those from formulas (1) and (2) with V
B
is replaced by V
R1
, so that when a reverse voltage which is about the breakdown voltage V
B
is applied over the whole voltage sustaining layer, the maximum field is E
C
and the minimum field is E
C
/3, where the locations of the maximum field are not only at the p
+
-n(or n
+
-p) junction, but also at the points of each p(or n) island nearest to the n
+
-n(or p
+
-p) junction; the locations of the minimum field are not only at the n
+
-n(or p
+
-p) junction, but also at the points of each p(or n) island nearest to the p
+
-n(or n
+
-p) junction. An example of the structure of a VDMOST using a voltage sustaining layer of this invention with n=2 is shown in FIG.
3
A and the field profile under a reverse voltage of V
B
is shown in FIG.
3
B. Apparently, in such a condition, V
B
=2WE
C
/3, where W is the total thickness of the voltage sustaining layer.
It is easy to prove that the above structured voltage sustaining layer including a plurality of floating regions is fully depleted under a reverse bias voltage about V
B
/2. The flux due to the charges of the ionized donors (or acceptors) under the p(or n) islands are almost totally terminated by the charges of the p(or n) islands. The maximum field is then 2E
C
/3 and the minimum field is zero, the locations of the maximum field as well as the locations of the minimum field are the same as those under a reverse bias voltage of V
B
.
Apparently, the p(or n) islands make the field not to be accumulated throughout the whole voltage sustaining layer. For a given value of breakdown voltage V
B
, the doping concentration N
D
can be higher than that in a conventional voltage sustaining layer and the specific on-resistance is much lower than that in a conventional voltage sustaining layer.
Suppose that there are n sub-layers in a voltage sustaining layer. Then, each sub-layer can sustain a voltage of V
B
, where V
B
is the breakdown voltage of the total voltage sustaining layer. Obviously, instead of (3), the relation of R
on
and V
B
of this invention is
R
on
=
n
×
0.83
×
10
-
8
(
V
B
/
n
)
2.5
Ω
·
cm
2
=
0.83
×
10
-
8
V
B
2.5
/
n
1.5
Ω
·
cm
2
(
5
)
Compared to formula (3), it can been seen that the on-resistance of a voltage sustanining layer having n sub-layers is much lower than that of a conventional one.
The inventor has experimented and obtained remarkable results, which show that the on-resistance of a semiconductor device using a voltage sustaining layer with n=2 of this invention is at least lower than ½ of that of a conventional one with the same breakdown voltage, although the real value of R
on
of a voltage sustaining layer having floating islands is a little higher than the value calculated from expression (5) when n<3, due to the effect that the current path is narrowed by the p-type floating islands. Besides, for minimizing R
on
, the optimum value of N
T
is slightly different with the expression (4), due to that the negative charges of p-type floating islands are concentrated in the p-regions instead of being uniformly distributed on a plane, whereas these negative charges are used to absorb the flux of ionized donors below that plane.
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patent: 4868624 (1989-09-01), Grung et al.
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patent: 5219777 (1993-06-01), Kang
patent: 5389815 (1995-02-01), Takahashi
patent: 5418376 (1995-05-01), Muraoka et al.
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patent: 5438215 (1995-08-01), Tihanyi
patent: 5519245 (1996-05-01), Tokura et al.
patent: 5572048 (1996-11-01), Sugawara
patent: 6011298 (2000-01-01), Blanchard
patent: 6066878 (2000-05-01), Neilson
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Microelectron, Reliab. vol. 24
Nadav Ori
Robinson Richard K.
Third Dimension (3D) Semiconductor
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