Static information storage and retrieval – Powering
Reexamination Certificate
2001-10-30
2004-02-10
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Powering
C710S100000, C714S037000
Reexamination Certificate
active
06690612
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage supply arrangement for a semiconductor device, particularly a semiconductor memory arrangement, with a controller and a bus system, which is connected on one side to the controller and on the other side, by way of a terminating resistor, to a terminating voltage supply, and to which the semiconductor memory arrangement is connected.
DE 44 45 846 A1 describes a circuit arrangement for the termination of a line leading to an integrated CMOS circuit. As the terminating resistor, a field-effect transistor is disposed in the integrated circuit. A p-channel FET is used, because the total supply voltage equals 0 V.
DE 43 22 658 A1 describes a terminating resistor circuit for a bus line in which a current source line, a signal line, and a grounding line are connected between computer devices via respective terminations. An input terminal of a controller is connected to the current source line, and the termination is provided between the output termination of the controller and the signal line. A Zener diode is located between the output terminal and the grounding line in such a way that the cathode terminal and the anode terminal are connected to the output terminal of the controller and the grounding line, respectively.
FIG. 2
represents an existing voltage supply arrangement for a semiconductor memory arrangement
1
composed of DRAMs D
1
, D
2
, . . . , Dn. This semiconductor memory arrangement
1
is connected to a bus system
2
, which is located on a printed circuit board PCB. This bus system
2
is connected at one end to a memory controller MEMC, specifically a driver DRV and a receiver REC. Some other semiconductor device can be connected to the voltage supply arrangement instead of a semiconductor memory arrangement.
At its other end on the output side, the bus system
2
comprises an external terminating resistor Rterm which is provided on a printed circuit board PCB in SMD technology and additionally connected to an external voltage supply Vtt that lies between the potential VSS and this external terminating resistor Rterm. This external voltage supply Vtt can be a transformer with a voltage regulating element. The terminating voltage which is delivered by the external voltage supply Vtt is set such that an input/output circuit—that is, an I/O circuit I/O for the memory controller MEMC and the DRAMs D
1
, D
2
, . . . , Dn which drives the semiconductor memory arrangement
1
via the bus system
2
—is at a suitable operating point for the operation. To accomplish this, the terminal resistor Rterm absorbs a wave sent over the bus system
2
by the memory controller MEMC or the DRAMs D
1
, D
2
, . . . , Dn and is thereby rated such that its resistance value corresponds to the characteristic impedance of the line of the bus system
2
.
By virtue of the external construction of the terminating resistor Rterm and terminating voltage supply Vtt, the desirable progressive increase of the packing density of the voltage supply arrangement for the semiconductor memory device
1
is limited not by the memory controller MEMC or the bus system
2
, but rather by the external wiring of this terminating resistor Rterm and voltage supply Vtt. In other words, it is impossible to achieve higher packing densities owing to this external wiring, which consumes a large amount of space.
A further disadvantage of the existing voltage supply arrangement is that the terminating resistor Rterm is mounted on the printed circuit board PCB by the SMD technique. As a consequence of the SMD assembly, the parasitic effects of the terminating resistor Rterm effectuate a reduction of the terminating bandwidth.
SUMMARY OF THE INVENTION
It is thus the object of the invention to lay out a voltage supply arrangement for a semiconductor memory arrangement wherein the terminating resistor and the terminating supply voltage are extremely stable, so that parasitic events in the terminating resistor are practically precluded.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory system including a controller; a bus system having a first side that is connected to the controller; and a semiconductor memory configuration including a plurality of DRAMs that are connected to the bus system. Each one of the plurality of the DRAMs includes a terminating resistor integrated therein and a terminating voltage supply integrated therein. The plurality of the DRAMs include a furthest away DRAM that is connected to the bus system at a location that is further away from the controller than any others of the plurality of the DRAMs. Only the terminating voltage supply of the furthest away DRAM and the terminating resistor of the furthest away DRAM are active. The terminating resistor of the furthest away DRAM connects the terminating voltage supply of the furthest away DRAM to a second side of the bus system.
The semiconductor memory arrangement consists of a plurality of DRAMs, with a terminating resistor and a terminating voltage supply integrated in each DRAM. But in this type of semiconductor memory arrangement consisting of a plurality of DRAMs, only the terminating voltage supply and the terminating resistor of the most suitable DRAM with respect to the bus, namely the DRAM most remote from the memory controller on the bus system, are active. It is possible to furnish all DRAMs with a terminating resistor and a terminating voltage supply, so that the DRAMs can be produced in an identical manner. When the DRAMs are then connected to the bus system, an appropriate DRAM with respect to the bus, namely the last DRAM on the bus system, taking as the starting point the memory controller, is active with respect to its terminating resistor and terminating voltage supply, whereas in all other DRAMs the terminating resistor and terminating voltage supply remain inactive.
This way, the terminating resistor and the terminating voltage supply are integrated into the semiconductor memory arrangement, so that an external wiring for the terminating resistor and terminating voltage supply can be forgone.
As a consequence of the integration of the terminating resistor and the terminating voltage supply into the individual DRAMs, or into the semiconductor memory arrangement generally, parasitic events are reduced, and ground bounce effects may also be drastically reduced. Besides this, the packing density can be substantially increased, there no longer being any limitation resulting from an external wiring for the terminating resistor and terminating voltage supply.
REFERENCES:
patent: 6184737 (2001-02-01), Taguchi
patent: 6271704 (2001-08-01), Babcock et al.
patent: 6308232 (2001-10-01), Gasbarro
patent: 6357018 (2002-03-01), Stuewe et al.
patent: 6438012 (2002-08-01), Osaka et al.
patent: 6480409 (2002-11-01), Park et al.
patent: 43 22 658 (1994-01-01), None
patent: 44 45 846 (1996-06-01), None
Gall Martin
Schaefer Andre
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