Voltage supply circuit in a semiconductor memory device

Details Voltage supply circuit in a semiconductor memory device Voltage supply circuit in a semiconductor memory device

2000-03-06

2001-05-29

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Powering

C365S205000, C365S230030, C365S196000

Reexamination Certificate

active

06240036

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a voltage supply circuit which supplies an operational voltage to sense amplifiers in a semiconductor memory device.
BACKGROUND OF THE INVENTION
Memory cell arrays MCA
1
. . . MCAm, sense amplifier arrays SAA
1
. . . SAAm and a voltage supply circuit
600
are shown in FIG.
7
.
A memory cell array MCAi (1≦i≦m) includes a plurality of memory cells and a plurality of bit line pairs. Each A bit line pair is connected to a memory cell and is provided with a data stored in the memory cell.
A sense amplifier array SAAi includes a plurality of sense amplifier circuits. Each sense amplifier circuit is connected to one of the bit line pairs in the MCAi and amplifies a voltage difference between the bit line pair.
The voltage supply circuit
600
supplies an operational voltage for the sense amplifier circuits in the sense amplifier arrays SAA
1
. . . SAAm. The voltage supply circuit
600
is comprised of an operational amplifier circuit
601
and a p-channel type MOS transistor
603
. An output terminal of the operational amplifier
601
is connected to a gate electrode of the MOS transistor
603
. A source of the MOS transistor
603
is connected to a node which receives a power supply voltage from an outside power supply. A drain of the MOS transistor
603
is connected to conductive lines. Each conductive line is located in one of the sense amplifier arrays and is connected to the sense amplifier circuits for supplying the operational voltage.
A first input terminal of the operational amplifier circuit
601
is connected to a reference voltage Vr which is a substantially constant voltage and a second input terminal is connected to the drain of the MOS transistor
603
.
In the semiconductor memory device mentioned above, if a voltage on the drain of the MOS transistor
603
becomes lower than the reference voltage Vr because of a current consumption in the sense amplifier array, the MOS transistor
603
turns on in response to a control signal which is provided from the output terminal of the operational amplifier
601
. Then, the voltage on the drain is raised.
On the contrary, if a voltage on the drain of the MOS transistor
603
becomes higher than the reference voltage Vr, the MOS transistor
603
turns off in response to the control signal. Then, the voltage on the drain gradually falls because of the current consumption in the sense amplifier array. If the voltage becomes lower than the reference voltage Vr, the operation mentioned above is repeated.
Therefore, the voltage on the drain of the MOS transistor
603
, that is the voltage on the conductive lines which supply the operational voltage to the sense amplifier circuits, is regularly maintained.
However, as the drain of the MOS transistor
603
is connected to a large number of sense amplifier arrays (the conductive lines), an undesirable delay can occur between sense amplifier arrays which are located in the vicinity of the drain and sense amplifier arrays which are located distant from the drain. This delay is caused by parasitic resisters, parasitic capacitors and the current consumption in the sense amplifier arrays.
This delay is undesirable in that it adversely influences a high speed operation in the semiconductor memory device. Particularly, in a dynamic random access memory which requires the highest speed, such delays may be a serious problem.
SUMMARY OF THE INVENTION
The object of the invention is to provide a semiconductor memory device which is capable of reducing a delay between a voltage supply circuit and a plurality of sense amplifier arrays.
To achieve the object, according to one aspect of the invention, a voltage supply circuit includes a plurality of MOS transistors, where each transistor is located between a power supply and one sense amplifier array.
According to another aspect of the invention, a voltage supply circuit is connected to one end of a conductive line which crosses a sense amplifier array and supplies an operational voltage to sense amplifier circuits therein, and the voltage supply circuit is connected to a reference voltage and a voltage on another end of the conductive line.
According to the present invention, it is possible to supply a stable operational voltage to the sense amplifier circuits in each sense amplifier array. A high speed operation can thus be realized.


REFERENCES:
patent: 5875145 (1999-02-01), Yamasaki et al.
patent: 5917765 (1999-06-01), Morishita et al.
patent: 5956278 (1999-09-01), Itou
patent: 5963475 (1999-10-01), Choi et al.
patent: 5966341 (1999-10-01), Takahashi et al.
patent: 6104641 (2000-08-01), Itou
patent: 410199241 (1998-07-01), None

Affiliated with

Also associated with

Rating

Voltage supply circuit in a semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Voltage supply circuit in a semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage supply circuit in a semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2441569