Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-10-29
2004-09-28
Berhane, Adolf (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
Reexamination Certificate
active
06798181
ABSTRACT:
The present invention relates to a circuit arrangement of transistors, particularly of JFETs, for use in supply circuits, particularly for high voltage integrated circuits (ICs).
According to the prior art such a circuit comprises a transistor connected between a high voltage supply and a load, e.g. a capacitor, and has its gate connected to ground to dissipate the multiplication current to ground. This leads to dissipation without any use.
It is an object of the invention to provide a supply circuit with a reduced dissipation and/or (multiplication) current loss. To this end, the invention provides a supply circuit as defined in the independent claims. Advantageous embodiments are defined in the dependent claims.
According to one aspect of the invention, there is provided a circuit comprising a first transistor, preferably a JFET, connected in series to a second transistor, also preferably a JFET, wherein the gate of the first transistor is connected to the source of the second transistor and is not connected to ground. The gate of the second transistor is preferably connected to ground.
Preferably the transistors are JFET transistors and at least the first JFET transistor is advantageously formed by a silicon on insulator (SOI) integration technology, for example as described in applicant's non-prepublished European application 99 204 404.0.
According to a preferred embodiment the first transistor is a high voltage JFET and the second transistor is a low voltage JFET. This circuit configuration is particularly advantageous when used to regulate the voltage to charge a capacitor and is applicable to lighting IC and power supply applications. The circuit is substantially multiplication independent.
The unique circuit configuration reduces the power loss through the ground connection of the gate of the second transistor because multiplication current from the gate of the first transistor bypasses the second transistor and is fed directly into the current path of the source of the second transistor.
For a better understanding of the present invention and to show how it may be carried into effect, reference will now be made, by way of example, to the accompanying drawings.
REFERENCES:
patent: 4686449 (1987-08-01), Jeffrey et al.
patent: 4760284 (1988-07-01), Taylor
patent: 5220530 (1993-06-01), Itoh
patent: 5285369 (1994-02-01), Balakrishnan
patent: 5359256 (1994-10-01), Gray
Berhane Adolf
Koninklijke Philips Electronics , N.V.
Ure Michael J.
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