Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Accelerating switching
Reexamination Certificate
2002-11-05
2004-12-21
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Accelerating switching
C327S534000, C327S544000, C713S323000
Reexamination Certificate
active
06833748
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a voltage supply circuit, and more particularly to, a voltage supply circuit capable of improving the operating speed while lowering a static power.
2. Description of the Prior Art
FIG. 1
is a circuit diagram of a conventional voltage supply circuit.
As shown in
FIG. 1
, the voltage supply circuit includes a standby mode bias supply unit
120
for controlling a high voltage level power supply voltage VEXT externally applied to be a high voltage level standby power supply voltage VDD of a given level, depending on a standby control signal STA for a standby operation in a standby mode, and then supplying the controlled voltage to an internal circuit
100
; and an active mode bias supply unit
130
for controlling the high voltage level power supply voltage VEXT externally applied to be an active mode power supply voltage V
AH
having a lower level than a standby mode power supply voltage V
SH
depending on an active control signal ACT for a normal operation in an active node and then supplies the controlled voltage to the internal circuit
100
.
The standby mode bias supply unit
120
includes a switching means S
11
connected between a terminal of the external high voltage level power supply voltage VEXT and a high voltage level power supply voltage node Q
11
of the internal circuit
100
being an output terminal, and a compare means A
11
for comparing a voltage of the high voltage level power supply voltage node Q
11
and a high voltage level reference voltage V
refSH
of a standby mode to control the switching means S
11
, depending on the standby control signal STA.
The active mode bias supply unit
130
includes a switching means S
12
connected between the terminal of the external high voltage level power supply voltage VEXT and the high voltage level power supply voltage node Q
11
of the internal circuit
100
being the output terminal, and a compare means A
12
for comparing the voltage of the high voltage level power supply voltage node Q
11
and the high voltage level reference voltage V
refAH
of an active mode to control the switching means S
12
, depending on the active control signal ACT.
A capacitor C
11
for preventing a riffle phenomenon is connected between the high voltage level power supply voltage node Q
11
and the terminal of an external low voltage level power supply voltage.
In a standby mode, the voltage supply circuit constructed above controls the external high voltage level power supply voltage VEXT to be a standby mode voltage V
SH
of a high voltage level depending on the standby control signal STA and then applies the controlled voltage to the internal circuit
100
via the high voltage level power supply voltage node Q
11
. At this time, the standby mode voltage V
SH
is also applied to a well region in which a transistor is formed, via the first back bias terminal Q
12
of the internal circuit
100
.
In an active node, the voltage supply circuit controls the high voltage level power supply voltage VEXT to be the active mode power supply voltage V
AH
of a high voltage level that is lower than the high voltage level power supply voltage V
refSH
of a standby mode, depending on the active control signal ACT, and then applies the controlled voltage to the internal circuit
100
through the high voltage level power supply voltage node Q
11
. At this time, the active mode power supply voltage V
AH
is also applied to a well region in which a PMOS transistor is formed, via the first back bias terminal Q
12
of the internal circuit
100
.
The external low voltage level power supply voltage VSS is applied to the internal circuit
100
through the low voltage level power supply voltage node Q
13
and is also applied to a well region in which a NMOS transistor is formed via a second back bias terminal Q
14
of the internal circuit
100
.
The internal circuit
100
generates a plurality of output signals OUT
1
~OUTn depending on a plurality of input signals IN
1
~INn. The output signal only OUT
1
shown in the drawing is outputted as an output signal Tx that is stabilized through the output buffer
110
having a PMOS transistor P
11
and a NMOS transistor N
11
.
In the standby mode, the output buffer
110
employs the standby power supply voltage V
SH
of the high voltage level and an external low voltage level power supply voltage V
SS
, which are applied through the high voltage level power supply voltage node Q
11
and the third node Q
13
, as the power supply. At this time, the standby power supply voltage V
SH
is applied to the well region in which the PMOS transistor P
11
is formed via the first back bias node Q
12
. Also, the external low voltage level power supply voltage V
SS
is applied to the well region in which the NMOS transistor N
11
is formed via the second back bias node Q
14
.
Further, in the active node, the output buffer
110
employs the active power supply voltage V
AH
of the high voltage level and the external low voltage level power supply voltage V
SS
, which are applied through the high voltage level power supply voltage node Q
11
and the third node Q
13
, as the power supply. At this time, the active power supply voltage V
AH
is applied to the well region in which the PMOS transistor P
11
is formed via the first back bias node Q
12
. Also, the external low voltage level power supply voltage V
SS
is applied to the well region in which the NMOS transistor N
11
is formed via the second back bias node Q
14
.
As described, the conventional voltage supply circuit controls the external high voltage level power supply voltage VEXT to be the standby power supply voltage V
SH
or the active power supply voltage V
AH
of the high voltage level in order to use the controlled voltage as the power supply, and also uses the external low voltage level power supply voltage V
SS
intact.
Due to this, there is a problem that noise due to ground bouncing is increased depending on a switching operation of the internal circuit
100
. In addition, as the back bias voltage applied to the transistor of the internal circuit
100
is fixed, the threshold voltage could not be varied using a body effect.
Therefore, in order to use the body effect, it is required that the concentration of doping in a process of manufacturing a transistor having a low threshold voltage be lowered. For this purpose, there are problems that additional mask is required, the number of process is increased and the production cost is increased.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is to provide a voltage supply circuit capable of reducing a dynamic power, compensating for an operating speed and reducing a static power, in a way that a swing width of a signal is made small when the circuit is driven by together applying an internal power supply voltage dropped from an external power supply and a raised internal ground voltage to an internal circuit, a threshold voltage is lowered by varying a back bias of a transistor when the internal circuit is driven at a low voltage, and the amount of current flowing at a voltage of below a sub-threshold voltage is minimized by raising the threshold voltage in a standby mode.
In order to accomplish the above object, a voltage supply circuit according to the present invention, is characterized in that it comprises a circuit that operates separately in a standby mode and in an active mode, a standby mode bias supply unit that controls each of an external high voltage level power supply voltage and an external low voltage level power supply voltage to be a given voltage level, depending on a standby control signal if the circuit is in the standby mode, and then supplying the controlled voltage to the circuit; and an active mode bias supply unit that reduces the width of the level between the external high voltage level power supply voltage and the external low voltage level power supply voltage, depending on an active control signal if the circuit is in the a
Callahan Timothy P.
Englund Terry L.
Hynix / Semiconductor Inc.
Piper Rudnick LLP
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