Voltage step-up circuit

Details Voltage step-up circuit Voltage step-up circuit

1996-04-19

1999-03-30

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327313, 327540, H03K 301, H02M 318

Patent

active

058894276

ABSTRACT:
A parallel connection of an enhancement type nMOS transistor and an enhancement type pMOS transistor is connected between an input terminal receiving a clock signal and a capacitor. The pMOS transistor is turned on and off in dependece on an output of a power supply voltage detector, so that a signal transmission path between the input terminal and the capacitor, as the clock signal is at a high level, has a switched position at a side of the nMOS transistor when the power supply voltage is high, and a switched postiion at a side of the pMOS transistor when the power supply voltage is low. Due to a threshold drop effect of the nMOS transistor, a signal amplitude of a high level is limited to an output level of a limiter minus a threshold voltage of the nMOS transistor, reducing a charge-discharge current of the capacitor.

REFERENCES:
patent: 4454571 (1984-06-01), Miyashita
patent: 4970409 (1990-11-01), Wada et al.
patent: 5072134 (1991-12-01), Min
patent: 5093586 (1992-03-01), Asari
patent: 5180928 (1993-01-01), Choi
patent: 5489870 (1996-02-01), Arakawa
patent: 5513091 (1996-04-01), Uchida et al.
patent: 5675279 (1997-10-01), Fujimoto et al.

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