Voltage stabilizer of embedded flash memory

Details Voltage stabilizer of embedded flash memory Voltage stabilizer of embedded flash memory

2001-04-09

2002-05-14

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200, C365S185210

Reexamination Certificate

active

06388923

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89124860, filed Nov. 23, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a voltage stabilizer. More particularly, the invention relates to a voltage stabilizer of an embedded flash memory.
2. Description of the Related Art
During the access of a flash memory, methods to indicate high threshold voltage and low threshold voltage are different. In one conventional method, a reference memory cell near a bit line voltage is compared with a selected memory cell. As shown in
FIG. 1
, a structure to compare the reference memory cell with the selected memory cell is illustrated. The structure comprises a bit line decoder
10
, a word line decoder
12
, a memory cell
14
, a current-to-voltage converter
16
, a reference word line
18
, a reference memory cell
20
, a reference voltage
22
and a voltage sense amplifier
24
.
An output of the bit line decoder
10
is coupled to a drain of the memory cell
14
. An output of the word line decoder
12
is coupled to a gate of the memory cell
14
. A source of the memory cell
14
is coupled to a ground voltage Vss. The output of the bit line decoder
10
is further coupled to the current-to-voltage converter
16
. A gate of the reference memory cell
20
at the other side is coupled to the reference word line
18
. A drain of the reference memory cell
20
is coupled to another bit line decoder (not shown), and a source thereof is coupled to the ground voltage Vss. A drain of the reference memory cell
20
is coupled to the reference voltage
22
. That is, both the drain of the reference memory cell
22
and the current-to-voltage converter
16
are coupled to the voltage sense amplifier
24
.
The above structure is used to detect the Vt distribution of memory cells on a chip, so as to trace the problems in fabrication process and to maintain a correct access. However, the structure is restricted by the variation range of the VDD. When the variation of the VDD exceeds ±10%, the word line voltage dependent on the VDD has a significant variation. Thus, the reference voltage bias node applied to the voltage sense amplifier
24
is shifted to cause an error access.
SUMMARY OF THE INVENTION
The invention provides a voltage stabilizer of an embedded flash memory. After receiving and processing an input voltage, a fixed voltage is output.
The stabilizer of the embedded flash memory comprises a voltage inspector, an annular oscillator, a frequency band interstitial voltage and stabilized clock generator, a switching controller, a charge pump, an NMOS transistor, a first resistor, a second resistor, a comparator, a PMOS transistor, a first capacitor and a second capacitor.
The voltage inspector receives a voltage to perform a range inspection, so as to select a value higher or lower than a standard value. When the value is higher than the standard value, the input voltage is output from a first output terminal. When the value is lower than the standard value, the input voltage is output from a second output terminal.
The annular oscillator generates a clock signal. The frequency band interstitial voltage and stabilized clock generator is coupled to the annular oscillator and the voltage inspector to generate a stabilized clock signal after receiving the clock signal, and to output a frequency band interstitial voltage to the voltage inspector as a power supply.
The switching controller is coupled to the first output terminal of the voltage inspector. When a voltage is input, the switching controller is conducted to output the fixed voltage to the final output terminal. The charge pump is coupled to the second output terminal of the voltage inspector, the frequency band interstitial voltage and stabilized clock generator to receive the stabilized clock signal. When the input voltage is lower than the standard. value, the input voltage is received and charged to a fixed voltage. The fixed voltage is output from the output terminal.
The NMOS transistor has a gate coupled to the second output terminal of the voltage inspector to receive the input voltage and a source coupled to the ground voltage. The first resistor has one terminal coupled to a drain of the NMOS transistor, and the other terminal coupled to one terminal of the second resistor. The other terminal of the second resistor is coupled to the final output terminal. The comparator comprises a first input terminal, a second input terminal, a third input terminal and an output terminal. The first input terminal is to receive the frequency band interstitial voltage, the second input terminal is coupled between the first and the second resistors, and the third input terminal is coupled to an output terminal of the charge pump to control the operation of the comparator. A gate of the PMOS transistor is coupled to the output terminal of the comparator. A source of the PMOS transistor is coupled to the output terminal of the charge pump. A drain of the PMOS transistor is coupled to the final output terminal. The first capacitor C
1
is coupled between the source of the PMOS transistor and the ground voltage. The second capacitor C
2
is coupled between the final output terminal and the ground voltage.
The frequency band interstitial voltage is 1.25 V. The resistance ratio of the first resistor R
1
and the second resistor R
2
is 1:3.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 6246613 (2001-06-01), Banks

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