Voltage sensitive isolation for static logic circuit

Details Voltage sensitive isolation for static logic circuit Voltage sensitive isolation for static logic circuit

1974-12-23

1976-03-16

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307214, 307215, 307251, 307270, H03K 1908, H03K 1936, H03K 1934, H03K 1704

Patent

active

039448487

ABSTRACT:
A static logic circuit utilizing transistors of the MOSFET type includes a high resistance load transistor, a low resistance logic network having a large self-loading capacitance, and a gating transistor connected in series between the network and the load device. The logic network controls the output voltage across a load capacitor by grounding the load transistor output for selected input data, and the gating transistor is biased to turn OFF when the voltage across the large self-loading capacitance exceeds a predetermined level, thereafter isolating the input network from the load capacitor and speeding up the output transition by decreasing the time required to charge the load capacitor.

REFERENCES:
patent: 3601627 (1971-08-01), Booher
patent: 3631261 (1971-12-01), Heimbigner
deSimone, "Low-Power MOSFET Decoder"; IBM Tech. Discl. Bull; Vol. 13, No. 1, pp. 260-261; 6/1970.
Reynolds et al., "Metal-Oxide-Semiconductor (MOS) Integrated Circuits"; Post. Off. Elect. Engrs. Jour. (G.B.), Vol. 63, pt. 2(7/1970); pp. 105-112.
West, "Practical Circuit Design Using M.O.S."; Design Electronics (p46); pp. 30-32, 37-38; 3/1971.
Fette, "Dynamic MOS -a logical choice", EDN/EEE (pub.); pp. ch(7-14); 11/15/1971.

Affiliated with

Also associated with

Rating

Voltage sensitive isolation for static logic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Voltage sensitive isolation for static logic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage sensitive isolation for static logic circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-294755