Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock
Patent
1978-11-20
1981-03-10
Anagnos, Larry N.
Electrical transmission or interconnection systems
Personnel safety or limit control features
Interlock
307DIG3, 365190, 365203, 365205, H03K 524, G11C 700
Patent
active
042556783
ABSTRACT:
A voltage sense circuit in which first and second parallel connections of complementary MOS transistors are connected between a pair of signal lines connected to memory cells and outputs of a flip-flop circuit for detecting a potential change of the signal line caused by data readout from an accessed memory cell. MOS transistors of one channel type in the parallel connections are adapted to precharge output node capacitors of the flip-flop circuit to a supply voltage level, while MOS transistors of the other channel type are adapted to couple complementary output voltage levels of the flip-flop circuit produced after the data readout and operation of the flip-flop circuit to the signal lines. Use of the parallel connections of complementary MOS transistors enables the application of a single power source for producing gate signals of these MOS transistors.
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Arzubi, "Sense Amplifiers for Capacitive Storage", IBM Tech. Discl. Bull., vol. 19, No. 2, pp. 407-408, 7/1976.
Furman et al., "Sense Latch Circuit for Memory Cells", IBM Tech. Discl. Bull., vol. 16, No. 9, pp. 2792-2793, 2/1974.
"Examination on the CMOS Sense Amplifier", Publication of the Electronics Communication Society, (Japan), 8/1977.
Asahi Hirozi
Ochii Kiyofumi
Suzuki Yasoji
Anagnos Larry N.
Tokyo Shibaura Denki Kabushiki Kaisha
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