Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-11-21
2003-05-20
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000, C341S136000, C341S145000, C341S172000
Reexamination Certificate
active
06567026
ABSTRACT:
BACKGROUND TO THE INVENTION
1. Field of the Invention
The present invention relates to a digital-to-analog converter (DAC), and in particular, to a voltage-scaling DAC.
2. Description of the Prior Art
DACs can, in general, be categorised as current-scaling, voltage-scaling or charge-scaling devices. A general discussion of DACs is provided in Grebene, Bipolar and MOS Analog Integrated Circuit Design. Jon Wiley & Sons, 1984, pp. 753 to 824.
Some voltage-scaling DACs produce an analog output voltage by selectively tapping a voltage divider resistor or other impedance string connected between the high and low terminals of a reference voltage, with the low terminal, generally being set at ground potential. These types of converters are commonly used as building blocks in MOS analog-to-digital conversion systems, where they function as the DAC subsection of a successive-approximation-type analog-to-digital converter. For an N-bit voltage-scaling DAC, a single resistor string comprising 2
N
identical resistors connected in series, is used as a potentiometer in which the voltage levels between successive resistors are sampled by means of binary switches. Replacing mechanical potentiometers and rheostats is an important and potentially very high volume application for these devices.
An alternative type of N-bit DAC which operates on the voltage-scaling principle is disclosed in U.S. Pat. No. 5,495,245 of Ashe. In the DAC of this U.S. specification; a pair of outer strings of series connected identical resistors are connected to respective reference voltage terminals. An inner string of equal value series connected resistors is connected at its respective opposite ends through a network of discrete outer switches to the respective outer strings. The outer switches are controlled by a decoder for moving the voltage applied across the inner string through the outer strings upwardly and downwardly within the range of the reference voltage. An analog output is selectively coupled through a network of inner switches to nodes between adjacent pairs of resistors of the inner string. The inner string of resistors corresponds to the least significant bits (LSBs) of the digital input signal, while the outer strings of resistors each correspond to the most significant bits (MSBs) of the digital input signal. Thus, the sum of the resistances of the inner string of resistors is equal to the value of one of the resistors of the outer strings. The decoder operates the inner switches for determining the analog output voltage corresponding to the LSBs of the digital input signal, while the decoder operates the outer switches for determining the analog output voltage corresponding to the MSBs of the digital input signal. The digital input signal is divided into an equal number of LSBs and MSBs. Thus, for an N-bit DAC where each voltage increment on the inner string corresponds to one LSB, for every 2
N/2
voltage increments, the position of the inner string is moved along the outer strings by one increment on the outer strings, which corresponds to one MSB. This is achieved by switching the appropriate switches of the outer switch networks. The switches of the outer switch networks typically are P and N-type, MOSFETs which are driven in anti-phase.
The DAC of this U.S. Specification suffers from a differential non-linearity (DNL) error every 2
N/2
codes of the digital input signal. In other words, the analog voltage output becomes non-linear each time the outer switches switch the inner string along the outer strings for each MSB. This results from the fact that the on-resistances of the respective switches of the outer switch networks vary with voltage level applied to the switches. The switches of the outer switch networks being MOS transistor switches, they have an inherent on-resistance, which varies with voltage level. Thus, even where the switches of the outer switch networks are kept as similar as possible to each other with their on-resistances being substantially similar, a differential non-linearity error still occurs every 2
N/2
codes of the digital input signal, since each of the switches of the outer switch networks is subjected to a different voltage level (due to the fact that the reference voltage is fed to the switches of the outer switch networks through the corresponding outer strings). In order to minimize this error, the switches of the outer switch networks have to be made relatively large in order to minimize their on-resistances so as to, in turn, minimize the variation in on-resistance resulting from voltage variation. This is undesirable, since it leads to an excessive space requirement on the integrated circuit chip.
There is therefore a need for DAC which minimises the effect of the on-resistance of switches of a switch network of a DAC.
SUMMARY OF THE INVENTION
According to the invention, there is provided a digital-to-analog converter (DAC) for an N-bit digital input signal comprising
a pair of voltage reference terminals for receiving a reference voltage,
an analog output terminal on which an analog output voltage derived from the reference voltage is developed,
first and second separate outer impedance strings of respective series connected impedance means defining a plurality of input taps,
first and second outer switch means for selectively coupling a selected one of the input taps of each of the corresponding first and second outer impedance string to a corresponding one of the reference voltage terminals,
an inner impedance string of respective series connected impedance means defining a plurality of output taps, the inner impedance string being connected in series with and between the respective first and second outer impedance strings,
an inner switch means for selectively coupling the output terminal to a selected one of the output taps, and
a control means responsive to the digital input signal for controlling the respective outer switch means for switching selectable portions of the corresponding outer impedance strings with the inner impedance string across the reference voltage terminals and for controlling the inner switch means for switching the output terminal to one of the output taps of the inner impedance string so that a voltage is developed on the output terminal corresponding to the digital input signal, the aggregate resistance of the portions of the outer impedance strings switched across the reference voltage terminals being substantially constant over the switching range, and the voltage level developed at the junction of the inner impedance string to one of the outer Impedance strings corresponding to one of the most significant bits (MSBs) and the least significant bits (LSBs) of the digital Input signal, and the voltage developed across the output terminal and the said junction of the inner impedance string with the said one of the outer impedance strings corresponding to the other of the MSBs and the LSBs of the digital input signal.
In one embodiment of the invention the respective first and second outer switch means comprise respective first and second outer switch networks, each switch network comprising a plurality of outer discrete switches, the number of switches in the respective outer networks corresponding to the number of input taps in the corresponding outer impedance string for individually coupling the respective corresponding input taps to the corresponding reference voltage terminal.
Preferably, the switches of the respective first and second outer switch networks are substantially identical to each other in the respective switch networks. Ideally, the switches of the respective first and second outer switch networks are all substantially identical to each other.
In one embodiment of the invention each switch of the respective first and second outer switch networks is provided by a P-type MOSFET and an N-type MOSFET driven in anti-phase. Alternatively, each switch of the respective first and second outer switch networks is provided by a single MOSFET type device.
Preferably, the first and second outer impedance strings each c
Analog Devices Inc.
Mai Lam
Tokar Michael
Wolf Greenfield & Sacks PC
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