Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-08-25
2001-07-17
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S148000, C327S094000, C327S095000
Reexamination Certificate
active
06262610
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to sample and hold circuits, and in particular, to voltage sample and hold circuits for low leakage charge pump circuits in phase lock loop applications.
2. Description of the Related Art
Referring to
FIG. 1
, charge pump circuits are often used in phase lock loop (PLL) applications for driving the voltage controlled oscillator (VCO) with a voltage filtered by a low pass loop filter Zf. Pump-up PU and pump-down PD signals, which are active low and high, drive a P-type metal oxide semiconductor field effect transistor (P-MOSFET) P
1
and an N-MOSFET, respectively. These signals PU, PD are active during the active state of a control signal &phgr;
1
. During the inactive state of this control signal &phgr;
1
, the charge pump drive signals PU, PD are disabled by opening switches S
1
U and S
1
D, and the charge pump transistors P
1
, N
1
are turned off by closing switches S
2
U and S
2
D. This places the output of the charge pump circuit, i.e., at the mutually connected drain terminals of the output transistors P
1
, N
1
, in a high impedance state. This disablement of the charge pump circuit is often done as a way to open the loop of the PLL to allow direct modulation of the VCO with some form of modulation signal MOD.
A problem with this, however, is the effect of leakage currents through the transistors P
1
, N
1
upon the voltage provided to the tuning input of the VCO. This voltage will gradually drift due to the charging or discharging of this node by way of the net leakage current Ioff which is the difference between the leakage current Ileakn of transistor N
1
and the leakage current Ileakp of transistor P
1
(Ioff=Ileakn−Ileakp). This is due to the typical mismatch between leakage currents for N-MOSFETs and P-MOSFETs and becomes worse as one transistor allows more leakage current than the other.
Typically, the dominant component of these leakage currents is the subthreshold currents of the transistors P
1
, N
1
. As MOSFETs are scaled down to smaller device geometries, subthreshold current becomes more substantial as compared to the normal “on” current.
One conventional technique for seeking to isolate the tuning input of the VCO is to introduce an in-line switch S
3
which is closed during application of the pump-up PU and pump-down PD signals and opened during the off, or high impedance, state of the charge pump circuit. However, one significant problem with this technique is that switch S
3
, when it is turned off, does not prevent the output node of the charge pump from drifting due to the net leakage current, Ioff. This results in a voltage difference across switch S
3
, which will cause the frequency of the output of the VCO to drift.
Referring to
FIG. 2
, one conventional technique for seeking to prevent unequal voltages from appearing across switch S
3
is to use a feedback amplifier A
1
in the form of a voltage follower for equalizing the voltages at the tuning input of the VCO and the output node of the charge pump circuit. When switch S
3
is opened, switches S
4
A and S
4
B are closed, thereby closing this feedback loop and equalizing the voltages on both sides of switch S
3
. (This is a technique taught by U.S. Pat. No. 4,544,854, issued Oct. 1, 1985, and entitled “Analog Switch Structure Having Low Leakage Current,” the disclosure of which is incorporated herein by reference.) However, this technique is not without its own problems. During the period that the voltages on either side of switch S
3
are being equalized by the feedback action of amplifier A
1
, the noise present at the input of the amplifier A
1
is now introduced to the tuning input of the VCO, thereby introducing yet another form of noise into the VCO output.
Accordingly, it would be desirable to have a technique for maintaining the voltage at the output node of a charge pump circuit, notwithstanding leakage currents affecting such node, without introducing additional noise.
SUMMARY OF THE INVENTION
A voltage sample and hold circuit in accordance with the present invention compensates for leakage currents affecting the sample node without introducing additional noise to such node. In a preferred embodiment, the voltage at the sample node is sampled immediately following the point in time at which such node is placed into a high impedance state. This voltage is stored across a capacitive circuit element and is buffered by a buffer amplifier and then fed back to such node during the holding period.
In accordance with one embodiment of the present invention, a voltage sample and hold circuit includes a circuit node, a buffer circuit, a charge storage circuit and a switching circuit. The circuit node is configured to convey a node voltage and a hold voltage. The buffer circuit is configured to receive and buffer a sample voltage and in accordance therewith provide the hold voltage which is substantially equal to the sample voltage. The charge storage circuit, coupled to the buffer circuit, is configured to receive and store charge in accordance with the sample voltage and in accordance therewith maintain the hold voltage. The switching circuit, coupled between the circuit node and the buffer circuit, is configured to receive at least one switch control signal and in accordance therewith sample the node voltage, provide the sample voltage and convey the hold voltage.
In accordance with another embodiment of the present invention, a low leakage charge pump circuit includes a circuit node, a current source circuit, a current sink circuit, a buffer circuit, a charge storage circuit and a switching circuit. The circuit node is configured to convey a source current, a sink current, a node voltage and a hold voltage. The current source circuit, coupled to the circuit node, is configured to receive at least one source control signal and in accordance therewith provide the source current during a source time period. The current sink circuit, coupled to the circuit node, is configured to receive at least one sink control signal and in accordance therewith receive the sink current during a sink time period. The buffer circuit is configured to receive and buffer a sample voltage and in accordance therewith provide the hold voltage which is substantially equal to the sample voltage. The charge storage circuit, coupled to the buffer circuit, is configured to receive and store charge in accordance with the sample voltage and in accordance therewith maintain the hold voltage. The switching circuit, coupled between the circuit node and the buffer circuit, is configured to receive at least one switch control signal and in accordance therewith sample the node voltage, provide the sample voltage and convey the hold voltage.
These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.
REFERENCES:
patent: 3158759 (1964-11-01), Jasper
patent: 3304507 (1967-02-01), Weekes et al.
patent: 4063182 (1977-12-01), Besson
patent: 4302689 (1981-11-01), Brodie
patent: 4352070 (1982-09-01), Beauducel et al.
patent: 4544854 (1985-10-01), Ulmer et al.
patent: 4764689 (1988-08-01), Thommen
Lau Wai
Lo Steve
Olgaard Christian
Baker & McKenzie
Lam Tuan T.
National Semiconductor Corporation
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