Voltage regulator with reduced power loss

Details Voltage regulator with reduced power loss Voltage regulator with reduced power loss

2002-06-06

2003-11-18

Sterrett, Jeffrey (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S281000, C323S907000

Reexamination Certificate

active

06650097

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage regulator.
2. Description of the Related Art
A conventional voltage regulator will be described with reference to FIG.
2
.
FIG. 2
is a circuit block diagram showing an example of a configuration of the conventional voltage regulator.
As shown in
FIG. 2
, a voltage regulator
201
, which is provided with external terminals, namely, an input voltage terminal
102
, a GND terminal
103
and an output voltage terminal
104
, is constituted by a reference voltage circuit
105
capable of outputting a constant voltage, a voltage dividing circuit
106
capable of dividing in an appropriate proportion a voltage of the output voltage terminal
104
, an error amplifier circuit
107
capable of comparing two input voltages to adjust an output voltage, and an output circuit
108
capable of adjusting an impedance.
The error amplifier circuit
107
causes the output circuit
108
to adjust an impedance such that an input voltage from the voltage dividing circuit
106
is kept equal to an output voltage of the reference voltage circuit
105
. Therefore, the voltage regulator
201
can keep a voltage of the output voltage terminal
104
constant even if an input voltage fluctuates.
In
FIG. 2
, the voltage dividing circuit
106
is constituted by resistors, and the output circuit
108
is constituted by an enhancement PMOS transistor. Various external loads such as a CPU and a microcomputer are connected to the output voltage terminal
104
according to an application of the voltage regulator
201
. The voltage regulator
201
generates in the output circuit
108
a loss represented by the following expression (1).
Pt
=(
V
in−
V
out)×
I
out  (1)
Where Pt is a loss (W), Vin is an input voltage (V), Vout is an output voltage (V) and Iout is an output current (A).
When the input voltage is high and the output current is large (an impedance of an external load is low), the loss increases. Usually, an allowable loss is defined for a plastic package or the like in which a voltage regulator is implemented and a user sets conditions of use not to exceed the allowable loss. Most of the loss is generated in the form of heat.
However, in the conventional voltage regulator, if it is erroneously used in excess of an allowable loss, there are problems that characteristics of the voltage regulator are deteriorated and the regulator may be destroyed by generated heat. Thus, a user is required to a measurement for heat radiation and safety in order to cope with a case of the voltage regulator being erroneously used in excess of an allowable loss.
SUMMARY OF THE INVENTION
In order to solve the above-described problems, a voltage regulator of the present invention is provided with means for detecting a loss, with which the voltage regulator can detect an increase in a loss to automatically enter a protective operation and reduce the loss.
The voltage regulator of the present invention is provided with a loss detecting circuit that functions so as to lower an output voltage when a loss has increased. When the loss detecting circuit is activated, the output voltage falls to decrease an output current, reducing the loss. As a result, an automatic protective function against an excessive loss is added to the voltage regulator, whereby a voltage regulator with high safety can be realized in which its characteristics are not deteriorated and the regulator is not destroyed even if conditions of use are erroneously set.
According to the present invention, there is provided a voltage regulator comprising:
an error amplifier circuit that receives an output from a reference voltage generation circuit as one input;
an output circuit that is controlled by an output of the error amplifier circuit;
a voltage dividing circuit that is connected to the output circuit in series, the error amplifier circuit receiving a divided voltage from the voltage dividing circuit as the other input;
a first loss detecting circuit that is connected between the one input of the error amplifier circuit and a GND terminal; and
a second loss detecting circuit that is connected between an input voltage terminal of the output circuit and an output terminal of the error amplifier circuit.
Here, as the loss detecting circuit, there may be used a temperature detecting circuit in which a gate and a source of an enhancement PMOS transistor are electrically connected or a temperature detecting circuit in which a gate and a source of an enhancement NMOS transistor are electrically connected.


REFERENCES:
patent: 4146903 (1979-03-01), Dobkin
patent: 4298835 (1981-11-01), Rowe
patent: 4587476 (1986-05-01), Cushman
patent: 4800331 (1989-01-01), Vesce et al.
patent: 5621306 (1997-04-01), Ise
patent: 6300749 (2001-10-01), Castelli et al.

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