Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2002-01-16
2004-01-13
Han, Jessica (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S275000
Reexamination Certificate
active
06677737
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of voltage regulators and in particular to that of regulators with a low drop out.
2. Description of the Related Art
A low drop out (LDO) regulator made in the form of an integrated circuit may be used to provide, with low noise, a predetermined voltage to a set of electronic circuits from a supply voltage provided by a rechargeable battery. Such a supply voltage decreases in time and is likely to include noise due for example to the action of neighboring electromagnetic radiations on the battery-to-regulator connections. The regulator is said to have a low drop out since it provides a voltage close to the supply voltage.
FIG. 1
schematically shows a conventional low-drop out regulator. The regulator includes an output terminal O intended for being connected to a load R. Load R, essentially resistive, represents the input impedance of the set of the circuits supplied by the regulator. For simplicity, it is considered hereafter that load R is a resistor. The regulator includes an operational amplifier
2
having an inverting input IN
−
connected to a positive reference voltage Vref and having a non-inverting input IN
+
connected to terminal O by a feedback loop. Voltage Vref is generated in a known manner by a constant voltage source (not shown) with a high output impedance. Amplifier
2
is supplied between a positive supply voltage Vbat provided by the battery and a ground voltage GND. The output of amplifier
2
is connected to the gate of a P-channel MOS power transistor T
1
having its drain connected to output terminal O and its source connected to voltage Vbat. Transistor T
1
is of MOS rather than bipolar type, especially to minimize the difference between output voltage Vout of terminal O and supply voltage Vbat. A charge capacitor C is arranged between output terminal O and voltage GND.
The regulator maintains voltage Vout of output terminal O to a value equal to reference voltage Vref. Any variation in voltage Vbat translates as a variation in voltage Vout, which is transmitted by the feedback loop on input IN
+
. When the regulator operates properly, the variation in the voltage of terminal IN
+
causes the return of voltage Vout to voltage Vref. For this purpose, the regulator circuit, which forms a looped system between input IN
+
and terminal O, must form a stable system. For this system to be stable when looped, its open-loop gain must not exceed 1 when the phase shift is smaller than −180° (phase opposition between the system input and output).
FIG. 2
illustrates, according to frequency f, the variation in gain G and in phase shift &phgr; of the open-loop regulator between input IN
+
and terminal O. For low frequencies f, gain G is equal to static gain Gs of the open-loop regulator. The elements forming the regulator each have a gain which varies according to frequency. The cut-off frequency of an element having a gain that decreases as the frequency increases corresponds to a “pole” of the transfer function of the open-loop regulator. Each pole of the transfer function of the open-loop regulator introduces a drop by 20 dB per decade in gain G. Further, each pole of the transfer function of the open-loop regulator introduces a phase shift &phgr; by −90°. For simplicity, it is considered hereafter that the transfer function of the open-loop regulator only includes one main pole P
0
and one secondary pole P
1
. The frequency of main pole P
0
especially depends on the inverse of the product of the values of load resistance R and of capacitance C. The frequency of secondary pole P
1
especially depends on the gate impedance of transistor T
1
. The features of the elements forming the regulator are chosen so that, when phase shift &phgr; becomes equal to −180°, gain G is smaller than 1 (0 dB). In
FIG. 2
, pole P
0
is at a low frequency, pole P
1
is at a greater frequency than pole P
0
. For a frequency smaller than the frequency of pole P
0
, the gain is equal to static gain Gs of the open-loop regulator. Between poles P
0
and P
1
, the gain drops by 20 decibels per decade. Beyond pole P
1
, the gain drops by 40 decibels per decade. The phase shift drops from 0 to −90° at pole P
0
and from −90° to −180° at pole P
1
.
The voltage regulator provides a current IO to load R, while maintaining output terminal O to reference voltage Vref. For the regulator to be able to provide a strong current IO, transistor T
1
must be large. As a result, the gate capacitance of transistor T
1
is high. The output impedance of amplifier
2
is small to be able to control the gate of transistor T
1
. The current IA consumed by amplifier
2
depends on the output impedance of amplifier
2
and is high. The efficiency of the voltage regulator depends on ratio IO/(IA+IO). Thus, the efficiency of a conventional regulator is low when current IO is low, for example, when the circuits supplied by the regulator are in a stand-by mode. Many electronic appliances supplied by a rechargeable battery, such as cellular phones, must be able to remain in stand-by mode for a long time. A conventional voltage regulator is poorly adapted to such appliances.
A conventional way of increasing the regulator efficiency consists of increasing the output impedance of amplifier
2
to reduce current IA consumed by amplifier
2
. However, the value of static gain Gs of the regulator is in particular proportional to output impedance Zout of the amplifier. A strong output impedance Zout makes static gain Gs high and shifts the secondary pole towards low frequencies, which respectively shifts the gain curve upwards and the phase curve to the left and makes the regulator stability difficult to obtain.
FIG. 2
illustrates as an example gain and phase curves G′ and &phgr;′ of an open-loop regulator having previous pole P
0
, having a secondary pole at a frequency P
1
′ smaller than previous frequency P
1
, and having a static gain Gs′ greater than previous static gain Gs. Gain G′ is greater than 1 (0 dB) when phase shift &phgr;′ reaches −180°, which makes the regulator unstable.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention is to provide a voltage regulator having a high efficiency.
To achieve this embodiment, as well as others, the present invention provides a voltage regulator having an output terminal connected to a load, including an amplifier having its inverting input connected to a reference voltage, and its non-inverting input connected to the output terminal, a charge capacitor arranged between the output terminal and a first supply voltage, first and second voltage-controlled switches each arranged to connect a second supply voltage and the output terminal, and a control means adapted to provide a voltage depending on the output voltage of the amplifier to the gate of the first switch and, when the current flowing through the first switch reaches a predetermined threshold, to the gate of the second switch.
According to an embodiment of the present invention, the current running through the first switch is smaller than or equal to said predetermined threshold.
According to an embodiment of the present invention, the amplifier is supplied between the first supply voltage and the second supply voltage.
According to an embodiment of the present invention, the first and second voltage switches are MOS transistors of a first type, the gate of the second switch being wider than the gate of the first switch.
According to an embodiment of the present invention, the control means includes first and second impedances, a first terminal of each impedance being connected to the second supply voltage, first and second bipolar transistors having their collectors connected to a second terminal respectively of the first and second impedances, and to the gates respectively of the first and second switches, the base and the collector of the first transistor being interconnected, the b
Bernard Christophe
Hamon Cécile
Pons Alexandre
Iannucci Robert
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.A.
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