Voltage regulator with a constant current circuit and...

Electricity: power supply or regulation systems – In shunt with source or load – Using a three or more terminal semiconductive device

Reexamination Certificate

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Details

C323S226000, C323S270000, C323S274000

Reexamination Certificate

active

06696822

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a voltage regulator used for Integrated Circuit Card and a semiconductor integrated circuit (it is called simply IC hereinafter).
This application relies for priority on Japanese patent application, Serial Number 229374/2001, filed Jul. 30, 2001, which is incorporated herein by reference in its entirety.
2. Description of the Related Art
FIG. 2
is a system configuration figure showing an example of an integrated circuit card. This integrated circuit card has the internal logic part
2
. This internal logic part
2
has EEPROM
1
(it is a nonvolatile memory which can elegy erase data stored therein), and CPU (Central Processing Unit) and ROM. The EEPROM
1
is a memory for memorizing data, such as personal information. The CPU is the equipment for performing data processing.
Furthermore, this integrated circuit card has a band gap
4
and a voltage regulator
3
. The voltage regulator
3
adjusts a power-supply voltage VDD supplied from an external device, and supplies a constant voltage VREG to the internal logic part
2
. The band gap
4
generates a reference voltage VR used as the reference of the voltage VREG and a constant current control signal CS.
The conventional voltage regulator used for the integrated circuit card is shown in FIG.
3
(
a
) and FIG.
3
(
b
). A series type voltage regulator is shown in FIG.
3
(
a
), and a shunt type voltage regulator is shown in
FIG. 3
b.
The voltage regulator shown in FIG.
3
(
a
) has a differential amplification circuit A which has an inverted input terminal − to which the reference voltage VR is applied. An output of the differential amplification circuit A is connected to a gate of a P type MOS transistor M
1
. A power-supply voltage VDD is applied to a source of the transistor M
1
and a drain of the transistor M
1
is connected to an output node N
1
. A voltage divider circuit which comprised of a resistor R
1
and a resistor R
2
is connected between the output node N
1
and a ground potential GND. Comparison voltage VC generated from the voltage divider circuit is given to an non-inverted input terminal + of the amplification circuit A.
The constant current control signal CS for generating constant current is given to the amplification circuit A. The signal of the output node N
1
is given to the amplification circuit A through a capacitor C
1
for phase compensation. A capacitor C
2
for voltage flat and smooth is connected between the output node N
1
and the ground potential GND.
In this voltage regulator, the voltage VREG at the output node N
1
is divided by the resistor R
1
and the resistor R
2
and is applied to the non-inverted input terminal + of the amplification circuit A as the comparison voltage VC (=VREGx R
2
/(R
1
+R
2
)). The voltage regulator receives the voltage VREG at the output node N
1
and the reference voltage VR applied to the inverted input terminal − of the amplification circuit A, and compares and amplifies the voltage difference between the voltage VC and the voltage VR.
Therefore, if the comparison voltage VC is higher than the reference voltage VR, the output voltage VO of the amplification at A goes high, internal resistance (resistance between a source and a drain) of the transistor M
1
increases, and the voltage VREG of the output node N
1
falls. Conversely, if the comparison voltage VC is lower than the reference voltage VR, the output voltage VO of the amplification circuit A becomes low, internal resistance of the transistor M
1
decreases, and the voltage VREG of the output node N
1
goes up.
By the above feedback operation, the voltage VREG of the output node N
1
is stabilized in the state where the comparison voltage VC coincides with the reference voltage VR. Therefore, it becomes VREG=VRx(1+R
1
/R
2
). In addition, since voltage change of the output node N
1
by the feedback operation returns to the amplification circuit A through the capacitor C
1
, it is prevented that the amplification circuit A will be in an oscillation state. Moreover, since a very small current change caused by a load connected to the output node N
1
is absorbed by the capacitor C
2
, the voltage VREG of the output node N
1
is maintained almost uniformly.
The voltage regulator shown in FIG.
3
(
b
) is replace with the transistor M
1
of the voltage regulator shown in FIG.
3
(
a
), and has a constant current circuit B which supplies constant current to the output node N
1
from the power-supply voltage VDD. Furthermore, this voltage regulator has an N type MOS transistor M
2
connected between the output node N
1
and the ground potential GND and controlled by the output voltage VO of the amplification circuit A.
In this voltage regulator, the constant current is always supplied to the output node N
1
by the constant current circuit B from the power-supply voltage VDD. Reduction of current which flows for the load connected to the output node N
1
rises voltage VREG of the output node N
1
. By this, the output voltage VO of the amplification circuit A rises, the internal resistance of the transistor M
2
decreases, and current which flows to this transistor M
2
increases. Conversely, an increase of current which flows for load reduces voltage VREG of the output node N
1
. By this, the output voltage VO of the amplification circuit A falls, the internal resistance of the transistor M
2
increases, and current which flows to this transistor M
2
decreases. It is controlled by such feedback operation so that the sum of current which flows for the load connected to the output node N
1
, and current which flows to the transistor M
2
becomes always constant, and the voltage VREG of the output node N
1
is stabilized.
However, the following subjects occurred in the conventional voltage regulator.
For example, in the series type voltage regulator, when the power-supply voltage VDD is 5V. the voltage VREG at the output node N
1
is 3V and the load current range between 0 and 10 mA, 0-10 mA current is supplied from the power-supply voltage VDD corresponding to the load current.
Therefore, the product of the voltage drop (2V) with the transistor M
1
and the load current is lost, and it is satisfactory from the viewpoint of power consumption.
However, since current supplied from the power-supply voltage VDD corresponded to load current, there is a problem enable it to analyze operation of the internal logic part of the integrated cat card, by acting as the monitor of the change of current supplied from the exterior.
When analysis technique, such as DPA/SPA (Differential Power Analysis/Simple Power Analysis), is used especially, there is a possibility that the problem that secret data which should be protected on security will be decoded from a power-supply current waveform may occur.
On the other hand, at the shunt type voltage regulator shown in FIG.
3
(
b
), since constant current always flows from the power-supply voltage VDD by the constant current circuit B, there is no possibility that an internal state may be decoded by the monitor of a power-supply current waveform. However, for this reason, regardless of actual load current, current which always exceeds 10 mA needed to be supplied and there is a problem in the viewpoint of power consumption.
Therefore, there are few increases in power consumption and the voltage regulator and IC with difficult analysis of operation of an internal logic circuit have been desired.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a voltage regulator includes a constant current circuit which is connected between an input node with which a power supply voltage is supplied and an output node to which a load is connected and which supplies constant current to the output node. The voltage regulator also includes a first tar which is provided in parallel to the constant current circuit and which flows insufficient current to the output node when current flowing through the load is larger

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