Voltage regulator output stage with low voltage MOS devices

Details Voltage regulator output stage with low voltage MOS devices Voltage regulator output stage with low voltage MOS devices

2007-04-03

2007-04-03

Easthom, Karl (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S270000, C323S280000, C323S281000

Reexamination Certificate

active

11008370

ABSTRACT:
Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.

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“A Low-Voltage Low Quiescent Current, Low Drop-Out Regulator”, by Rincon-Mora et al., IEEE Journal of Solid-State Circuits, vol. 33, No. 1, Jan. 1998, pp. 36-44.

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