Electricity: electrical systems and devices – Electrolytic systems or devices – Double layer electrolytic capacitor
Reexamination Certificate
2002-03-19
2003-06-17
Riley, Shawn (Department: 2838)
Electricity: electrical systems and devices
Electrolytic systems or devices
Double layer electrolytic capacitor
C323S272000, C323S284000, C323S285000, C713S322000
Reexamination Certificate
active
06580597
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a voltage regulator module for supplying power to a microprocessor and a CPU.
Conventionally, as a circuit configuration of a VRM (Voltage Regulator Module), which is a power supply for supplying power to a computer microprocessor or a large scale integrated circuit called CPU (Central Processing Unit), a multi-phase shift converter system has been proposed and has become popular. As an example thereof, JP-A-8-242577, “switching regulator” can be mentioned.
In the CPU, with the fine process advanced for a purpose of enhancing the processing performance, the core voltage has lowered to approximately 1.5 to 1.0 V. On the other hand, due to an increase in the number of transistors simultaneously used for computation operation by parallel processing software, the current consumption has increased to several tens to 100 A. Furthermore, according to contents of computation in the CPU, the current consumption changes momentarily and its current change rate (di/dt) becomes extremely as large as 300 to 1000 A/&mgr;s. Therefore, a low voltage, a large current, and a high current change rate responsibility are required of the VRM, which supplies power to the CPU.
A conventional technique for coping with the request is the multi-phase shift converter system. A VRM of this system will now be described by referring to FIG.
11
. In
FIG. 11
, reference numeral
20
denotes a DC (direct current) power source,
21
a
,
21
b
,
22
a
and
22
b
power MOSFETs,
23
a
and
23
b
smoothing coils,
24
a smoothing capacitor,
25
a load,
26
a
and
26
b
drive circuits, and
27
internal resistance of the capacitor. In the circuit of
FIG. 11
, power MOSFETs
21
a
and
22
a
are connected in series to the DC power source
20
. A filter including the smoothing coil
23
a
connected to a connection point between the power MOSFET
21
a
and the power MOSFET
22
a
, and the smoothing capacitor
24
forms a step-down converter. The power MOSFET
21
b
, the power MOSFET
22
b
and the smoothing coil
23
b
are also connected in the same way. The smoothing coil
23
a
and the smoothing coil
23
b
are connected on the load side. Gates of the power MOSFET
21
a
and the power MOSFET
22
a
are connected to the drive circuit
26
a
. Gates of the power MOSFET
21
b
and the power MOSFET
22
b
are connected to the drive circuit
26
b.
Operation of
FIG. 11
will now be described. As described above, a low voltage, a large current, and a high di/dt response are demanded of the load CPU
25
. For a steep load change, it is desirable to supply a current corresponding to high frequencies from the smoothing capacitor to the load. However, the internal resistor
27
of the capacitor exists in the smoothing capacitor
24
, and its value is comparatively large. Therefore, di/dt of the CPU load cannot be coped with, and the load voltage varies. This results in false operation of the CPU
25
.
In the VRM of the conventional technique, two or more converters are connected in parallel to improve the di/dt response of the current supplied from the converters. First, if the power MOSFET
21
a
turns on, a current flows from the DC power source
20
into the smoothing capacitor
24
through the smoothing coil
23
a
. If the power MOSFET
21
a
turns off and the power MOSFET
22
a
turns on, the current that has flown through the smoothing coil
23
a
flows in a source-drain direction of the power MOSFET
22
a
. On the other hand, the converter formed of the power MOSFETs
21
b
and
22
b
and the smoothing coil
23
b
also functions in the same way. If at this time the power MOSFET
21
a
and the power MOSFET
21
b
are made equal in switching frequency and deviated in switching phase by 180 degrees, then currents flowing through the smoothing coils
23
a
and
23
b
differ in phase by half the period. As compared with the case where only the MOSFETs
21
a
and
22
a
are activated, therefore, the ripple on the output current can be reduced to half. In the multi-phase shift converter system, it is thus attempted to obtain a high di/dt response by connecting n number of converters in parallel and shifting switching phases of the power MOSFETs of these converters 360°
by 360°
.
For obtaining a high di/dt response, however, two or more number of converters must be connected in parallel in the VRM of the conventional technique. It is possible to integrate power MOSFETs and the drive circuits. However, as many smoothing coils, which are difficult to be integrated, as the converters are needed. Therefore, the number of components is large, and the area of mounting becomes large. Furthermore, the conventional technique has a drawback that the cost also becomes high. Furthermore, if the distance between the converters and the load CPU becomes long, inductance of the wiring pattern increases and the change of the voltage caused by a change of the load current becomes non-negligible. In the conventional VRM having a large number of components, however, it is difficult to dispose the converters close by the load CPU.
SUMMARY OF THE INVENTION
An object of the present invention is to achieve a low voltage, a large current, and a high di/dt response in a voltage regulator module called VRM for supplying power to a CPU by mounting an electric double-layer capacitor having extremely low internal impedance close by the CPU.
In accordance with the present invention, a charge storage unit having at least two sets of positive electrode terminals ((+) terminals) and negative electrode terminals ((−) terminals) is provided as means for achieving the object. The charge storage unit is mounted and disposed in an internal region of a virtual globe having a length of a longer side of the load CPU as a radius thereof and the center of gravity of the load CPU as a center thereof.
The load as CPU is suitable for the case where it is activated by a clock frequency of at least 500 MHz, and the load CPU has a core voltage of 2 V or less, a rated current consumption of at least 50 A, and a current change rate of at least 150 A/&mgr;s. The number of (+) terminals may be equal to the number of (−) terminals. It is also effective to make the number of (+) terminals more than the number of (−) terminals by at least one, and use one of the (+) terminals to detect a voltage within the charge storage unit.
It is also effective as means for achieving the object to make the interval (pitch) of the (+) terminals and (−) terminals equal to the interval (pitch) of terminals of the integrated circuit and arrange the (+) terminals and (−) terminals alternately. In addition, from the viewpoint of component reduction and efficiency improvement, it is desirable that the voltage regulator module is a single-stage DC-DC converter that is supplied with a DC voltage of at least 13 V and that outputs a voltage of 2 V or less.
It is possible to mount the load CPU on an obverse side of a substrate and mount the charge storage unit on a reverse side of the substrate. It is also possible to mount the load CPU on the substrate in a silicon chip state, and mount the charge storage unit on the substrate. It is also possible that the length of a longer side of the charge storage unit is shorter than the length of a longer side of the integrated circuit, and a thickness of the charge storage unit exclusive of terminals is 5 mm or less. The charge storage unit can be implemented by an electric double-layer capacitor formed by mixing fine carbon fiber in active carbon, opposing graphite foils with the active carbon applied to one side thereof to each other, and interposing a separator impregnated with sulfuric acid between the graphite foils. It is desirable that the charge storage unit has a capacitance of at least 10 mF and an internal resistance of 1 m&OHgr; or less.
REFERENCES:
patent: 5982156 (1999-11-01), Weimer et al.
patent: 6081434 (2000-06-01), Kinoshita et al.
patent: 8-242577 (1996-09-01), None
Endo Morinobu
Kanouda Akihiko
Nohara Mikiya
Onda Kenichi
Saga Ryouhei
Hitachi , Ltd.
Riley Shawn
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