Voltage regulator incorporating a stabilization resistor and...

Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...

Reexamination Certificate

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C323S277000

Type

Reexamination Certificate

Status

active

Patent number

06580257

Description

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to voltage regulators, and more particularly, to a voltage regulator equipped with a device for limiting an output current therefrom.
BACKGROUND OF THE INVENTION
A voltage regulator is a four-pole electrical device interposed between a source of electrical power and an electrical circuit. The electrical circuit is called a load circuit, and is supplied by the electrical power source. The type of electrical power source may vary, for example, between a chemical cell that is non-rechargeable and a battery that is rechargeable. Power sources do not necessarily deliver a constant output voltage. The output voltage may depend, for example, on a state of depletion of the power source, especially in the case of a chemical cell, or on the current charge of a battery.
The load circuit may be an electronic circuit intended for any application, such as a mobile radio communications terminal powered by its own battery. A voltage regulator is used when the load circuit requires a constant supply voltage for its operation, although the power source delivers a voltage that is variable along its duration of use. The function of the voltage regulator is to receive an input voltage that is variable, and to deliver a power-supply voltage that is substantially constant.
The voltage regulator is a low-drop-out (LDO) type if it operates even when the voltage difference between the power source and the nominal power-supply voltage becomes significantly reduced. In general, a stabilization capacitor is placed in parallel with the load circuit at the output of the voltage regulator. When a voltage is applied to the load circuit, a transient condition then occurs, during which the current delivered by the voltage regulator momentarily exhibits a very high level that is very capable of damaging the power source. It is then necessary to make provisions for limiting the electrical current levels delivered by the voltage regulator. This limitation also prevents damage which might result from an accidental short-circuit occurring in the load circuit, or from a high leakage current in the stabilization capacitor.
Devices exist for limiting the current delivered by a voltage regulator, and especially devices incorporated into the regulator itself. These devices are also called short-circuit protection circuits. In the particular case of LDO regulators which deliver an electrical power controlled by a power transistor contained in these regulators, one short-circuit protection method includes reproducing, in a circuit branch added to the regulator, the level of the electrical current delivered to the load circuit. This reproduced current level is obtained by using an additional transistor which, to within a scale factor, recopies the level of the current delivered by the power transistor to the load circuit.
The short-circuit protection is achieved by a limitation of the current level delivered by the power transistor when the recopied current level in the added circuit branch becomes greater than a previously fixed threshold. This threshold is chosen to prevent any damage that too high a current level delivered to the load circuit might cause.
FIG. 1
is an electrical diagram of a linear voltage regulator
1
according to the prior art. The electrical power delivered to the load circuit
20
is controlled by a power transistor
2
. This transistor
2
may be a p-channel metal-oxide-semiconductor (PMOS) transistor, for example. The voltage regulator
1
receives a power supply voltage from an electrical power source
10
, the positive terminal E of which is linked to the source of the power transistor
2
. The drain of this transistor
2
is linked to the output terminal S of the regulator
1
. The other output terminal of the regulator
1
is linked to ground. The power source
10
and the load circuit
20
are also linked to ground.
The transistor
2
is controlled on its gate by the output of an operational amplifier
11
, which will now be referred to as an error amplifier. The error amplifier
11
is slaved by a feedback path starting from an intermediate node of a voltage-divider bridge
12
linked to the non-inverting input of this amplifier. The inverting input of the error amplifier
11
receives a reference voltage U
ref
that is fixed with respect to ground. The reference voltage U
ref
may be produced, for example, by a voltage source exploiting the forbidden band of a semiconductor material.
The voltage divider
12
is arranged in parallel with the load circuit
20
within the voltage regulator
1
. The voltage divider
12
includes, for example, two resistors connected in series. One resistor
12
a
is connected between the terminal S and the feedback node, and the other resistor
12
b
is connected between the feedback node and ground. The respective values R
a
, R
b
of these two resistors
12
a
,
12
b
are chosen as a function of the reference voltage U
ref
and of the desired power-supply voltage U, given that U=U
ref
*[(R
a
+R
b
)/R
b
].
A stabilization capacitor
21
is placed in parallel with the load circuit
20
, such as across its input. The capacitance of this stabilization capacitor
21
is 1 microfarad, for example.
The short-circuit protection circuit
100
of the voltage regulator
1
according to
FIG. 1
includes a recopy transistor
13
operating under conditions similar to those of the power transistor
2
. The illustrated recopy transistor
13
is also a PMOS transistor. The respective gates of these two transistors
2
,
13
are linked together, as are their sources which are connected to the positive terminal E of the electrical-power source
10
.
Under these conditions, the current level flowing in the transistor
13
recopies the current flowing in the power transistor
2
. The level of the recopied current is compared using a transistor
14
with a fixed reference current I
f
. The fixed reference current I
f
is produced by a current generator
15
placed between the drain of the recopy transistor
13
and ground. The transistor
14
is, for example, an n-channel metal-oxide-semiconductor (NMOS) transistor. The gate of the transistor
14
is connected between the drain of the recopy transistor
13
and the current generator
15
. The source of the transistor
14
is linked to ground, and its drain is linked to the positive terminal of the power source
10
via a resistor
17
.
Another PMOS transistor
16
has its gate linked to the drain of the NMOS transistor
14
, and its channel is connected between the positive terminal E of the power source
10
and the output of the amplifier
11
. This transistor
16
causes the voltage between ground and the gate of the power transistor
2
to rise when the level of the current recopied by the transistor
13
becomes greater than the level of the reference current I
f
. Thus, the current level delivered to the load circuit
20
and which is controlled by the power transistor
2
is limited.
One drawback of this layout lies in the fact that the electrical power corresponding to the recopied current level is dissipated within the voltage regulator itself, i.e., in the current generator
15
. This corresponds to electrical power delivered by the power source
10
that is lost with regards to the power supply for the load circuit
20
.
In the case of a battery, a voltage regulator and a load circuit that are integrated into a self-contained electrical device, such as a mobile radio communications terminal, for example, lost electrical power associated therewith reduces the endurance of the device. This reduction in the endurance represents an important drawback for the use of this type of short-circuit protection regulator.
A partial approach for recopying the current includes using a transistor
13
such that the scale factor for recopying the current level flowing in the power transistor
2
is small, or even very small. However, such an approach made in terms of the choice of the physical dimensions of the transistors
2
and
13
is a constraint that is

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