Voltage regulator for supplying power to internal circuits

Details Voltage regulator for supplying power to internal circuits Voltage regulator for supplying power to internal circuits

2000-09-11

2002-11-12

Sterrett, Jeffrey (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S267000, C323S271000, C323S282000

Reexamination Certificate

active

06479972

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage regulator for supplying power to internal circuits; more particularly, the invention relates to a voltage regulator capable of supplying power to the internal circuits of a DRAM IC.
2. Description of the Prior Art
The conventional regulator is often used to supply the sensing voltage (referred to as Vsa hereinafter) of bit lines in a DRAM IC.
First, the circuit structures of a prior art is explained as follows with reference to
FIG. 1A
, which shows a circuit diagram of the prior art. As shown in
FIG. 1A
, a operation amplifier
1
is connected to a PMOS transistor M
1
, which has input terminals
5
and
7
for receiving signals from the reference voltage and Vsa, respectively, such that the input terminal
7
is further connected to a node
3
to receive the voltage of the node
3
. The operation amplifier
1
is used for comparing the voltage of the node
3
(referred to as Vsa hereinafter) and a reference voltage. Take a 2.7V reference voltage as an example, when the Vsa is larger than 2.7V, the operation amplifier
1
will output a high voltage. signal. When the Vsa is lower than 2.7V, the operation amplifier
1
will output a low voltage signal. The source of the PMOS transistor M
1
is used for receiving the output of the external power supply Vdd (such that the Vdd equals 5V, for example), and the drain of the PMOS transistor M
1
is connected to a loading device Csa at the node
3
. The loading device Csa is connected between the node
3
and the ground. Wherein, the node
3
is connected to the input
7
of the operation amplifier
1
and outputs the Vsa, and the loading device Csa is a capacitor.
Next, the operation procedure of the conventional circuit will be described. As mentioned above, the Vsa supplies the sensing voltage of the bit lines in a DRAM IC. When the Vsa is larger than 2.7V, the output of the operation amplifier
1
may go higher and higher to decrease the Ids of the PMOS. transistor M
1
, wherein the Ids is a current that flows from the source of the PMOS transistor M
1
to the drain of the PMOS transistor M
1
, then less and less charge flows onto the Vsa. When the bit lines sensing current sunk from the Vsa, the Vsa will drop lower and lower, until it is lower than 2.7V, the output of the operation amplifier
1
will go lower to turn on the PMOS transistor M
1
to let more charge flowing onto the Vsa.
In other words, by using the operation amplifier
1
, the Vsa can be maintained at a stable level.
However, there are some problems in the structure of the conventional circuits.
The first problem in the conventional Vsa design is that the Vsa is affected by vdd. As shown in
FIG. 1B
, when Vdd gets higher. and higher and exceeds the speed that the operation amplifier M
1
can respond to, the supplying charge to the capacitor Csa, in a unit time, is also increased. Consequently, the charging speed of the capacitor Csa gets faster. Therefore, during the continuous charging-discharging process, the increasing Vsa will be too high, hence results in damage of the components of the circuit thereby. The second problem, when the Vsa is applied to sense the bit lines of DRAM, the Vsa is decreased. However, the Vsa of exceedingly low voltage will disable the operation of the DRAM IC. Moreover, because the sensing of a DRAM lasts only a certain period, the value of Vsa must be restored to the normal voltage value within the sensing period of the DRAM to avoid affecting the operation of the DRAM in the next sensing period. So it is important to decrease the recovery. time for Vsa to return to the normal voltage value quickly.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an internal power supply, which has a constant Vsa that do not vary with Vdd. And the internal power supply will raise the voltage level in advance after output to prevent the Vsa from dropping exceedingly low. Moreover, the recovery time of the Vsa is reduced.
To achieve the above-mentioned object, the present invention provides a voltage regulator to supply the power of the circuits in the DRAM IC. The voltage regulator process the voltage source from the external power supply by incorporating multiple buffers to prevent the internal power supply from being influenced by the, external power supply. Before supplying the power to DRAM, by means of increasing the voltage of the internal power supply the voltage of the internal power supply can be stopped from dropping exceedingly low, which will affect the operation of the DRAM IC. Also, a normal voltage level can be regained quickly. The speed for the voltage, to return to the normal voltage level can be achieved by changing the loading of the voltage regulator (excluding the loading of the bit lines) so that the variation of the voltage level during output is decreased as well as, the voltage variation. During charging, the decrease in the loading of the voltage regulator will decrease the recovery time.
Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.


REFERENCES:
patent: 5408172 (1995-04-01), Tanimoto et al.
patent: 5557193 (1996-09-01), Kajimoto
patent: 5889392 (1999-03-01), Moore et al.
patent: 5977755 (1999-11-01), Miki et al.
patent: 6084386 (2000-07-01), Takahashi et al.
patent: 6201374 (2001-03-01), Ater et al.

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