Voltage regulator for non-volatile memory with large power...

Details Voltage regulator for non-volatile memory with large power... Voltage regulator for non-volatile memory with large power...

2001-04-05

2002-09-10

Nguyen, Matthew (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

Reexamination Certificate

active

06448750

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to voltage regulators for use in the current supply to the drain on other electrodes of the memory transistors of a non-volatile memory integrated circuit.
BACKGROUND OF THE INVENTION
In using non-volatile memory (NVM) arrays, such as EPROMs, a relatively large current is required to be delivered to the drain electrodes of the transistor memory cells. This is usually done at a boosted voltage, called VPP (typically 4-7V), which is above the standard voltage supply, called VDD (typically 1.8-3.6V). The source of the boosted voltage is usually a charge-pump. A typical charge pump for a NVM array is shown for example, in U.S. Pat. No. 5,280,420. Typically, the boosted output voltage VPP of the pump has an AC ripple which is superimposed on the DC level. In many instances, a voltage regulator is used between the output of the charge pump and the NVM to eliminate AC ripple and fix the DC voltage irrespective of process/environment variations.
It is important that such a regulator has a high power supply rejection ratio (designated PSRR) so that the charge pump noise or ripple does not reach the NVM transistors, such as the drain electrodes of EPROM transistor memory cells, and affect the programming or erase characteristics of the memory cells. In addition, as the efficiency of the charge pump is typically 30%, it is important for the regulator to minimize the current consumption on the charge pump in order to conserve power.
A prior art regulator, which minimizes current consumption on the charge pump, is shown in FIG.
1
. In this regulator there is a differential amplifier gain stage, GM
1
, and an inverting amplifier gain stage, GM
2
. Both GM
1
and GM
2
receive as operating voltage the voltage VPP from the charge pump supply (not shown). Gain stage GM
1
is basically a differential amplifier whose inverted input is from a stable reference bias voltage source IP. The output of GM
1
is applied to the gate of GM
2
, which is shown as a P-channel MOS transistor (PMOS).
The boosted voltage VPP from the charge pump is applied to GM
1
as its operating voltage and is also applied to the source of GM
2
. The drain of GM
2
is connected to the reference potential (ground) through a voltage divider of two series connected resistors R
1
and R
2
. A capacitor (Cm), commonly called the “Miller capacitor”, is connected to the gate of GM
2
and the output of GM
1
at n
1
and to the upper end of the voltage divider R
1
and R
2
at n
2
. The capacitor Cm is used to stabilize the operation of GM
1
. A capacitor CL is across the voltage divider R
1
-R
2
to ground.
The load current, I
LOAD
, which is the current drawn by the memory cells of the NVM, is taken off at the drain of GM
2
at node n
2
, across the two resistors R
1
and R
2
to ground. The voltage output at n
2
is set by the ratio of R
1
and R
2
.
There is a feedback path fb from the junction of R
1
-R
2
to the non-inverting input of the differential amplifier gain stage GM
1
. When there is a large I
LOAD
, the gate of the PMOS driver GM
2
adjusts itself from the feedback voltage fb to provide an appropriate current. That is, for example, as I
LOAD
increases the feedback loop sets the operation point of GM
2
to drive higher current.
The circuit of
FIG. 1
has a poor PSRR. This is because the Miller capacitor (Cm, used to stabilize the amplifier), couples the gate of GM
2
to its drain at high frequencies. Since the load capacitor CL is coupled to ground, this means that at high frequencies the gate of GM
2
effectively will be coupled to ground. When VPP is noisy at the high frequencies, the gate to source voltage (Vgs) of GM
2
will change, and the noise will reach the output at n
2
. In general, in order to have a good PSRR, the gate electrode of GM
2
must be strongly coupled to the VPP source at all frequencies so that the Vgs of GM
2
remains constant.
FIG. 2
shows another prior art regulator circuit which has good PSRR but does not conserve current from the charge pump. Here, the output of a differential amplifier gain stage GM
1
feeds the gate electrode of an NMOS transistor driver GM
2
. The drain of GM
2
is connected to the output. Also connected to the output is PMOS transistor P
1
, which is configured as a current source to VPP, with its source node at VPP. The gate of P
1
is connected to the gate of the current mirror input PMOS transistor P
2
whose source also is connected to VPP. There is a stabilizing capacitor C
3
for the amplifier between the output of GM
1
and the drain of P
1
. PMOS transistor, P
1
, is configured as a current source for GM
2
. The gate of P
2
is connected to its drain and the drain is DC coupled to ground by a current source shown by the intersecting circle symbol. The gate of P
1
is strongly AC coupled to VPP through the transconductance characteristic (GM) of current mirror transistor P
2
.
Here, the differential stage GM
1
inverted input receives the reference voltage IP and its output is coupled to the gate of GM
2
. The drain node of GM
2
is connected to the drain node of P
1
and the GM
2
source node is connected to ground. There is a voltage divider R
1
-R
2
having one end connected to the junction of the P
1
drain node and GM
2
drain node and the other end to ground. A feedback path fb is between the junction of the R
1
-R
2
divider and the non-inverted input of GM
1
. A load capacitor CL is connected across R
1
-R
2
to ground.
The PSRR of the circuit of
FIG. 2
is determined by the characteristics of the current mirror P
1
-P
2
, such as its overdrive (Vgs-Vt or VDSAT) and transconductance (GM), as is known in the art. The PSRR of the circuit of
FIG. 2
is relatively good because the current source to VPP (P
1
) has both its gate node and source node strongly AC-coupled to VPP, such that its Vgs remains relatively constant at all frequencies. The problem with the circuit of
FIG. 2
is that the current in P
1
must always be greater than the maximum possible current in I
LOAD
. Thus, even when I
LOAD
is small, there is a significant current drain from the charge pump and VDD current is wasted.
OBJECTS OF THE INVENTION
An object of the invention is to provide a regulator for a NVM that exhibits both a high PSRR and minimal current consumption as compared to prior art regulators.
Another object of the present invention is to provide a high voltage VPP regulator having a differential stage that operates from a lower voltage VDD supply and an output stage connected to a VPP boosted supply.
An additional object is to provide a regulator to supply a boosted VPP voltage to a NVM, such as an EPROM, the regulator having an operational amplifier operating from a lower voltage VDD and receiving a feedback voltage from the load to adjust the current supply from a current mirror operating from VPP to control the load current.
BRIEF DESCRIPTION OF THE INVENTION
In accordance with the invention, a differential amplifier operating from the lower VDD voltage has one input connected to a reference bias voltage source. The amplifier output drives a gain stage that controls a current mirror operating from boosted voltage VPP, typically produced by a charge pump, and whose output is the load current that is supplied to the NVM transistor memory cells. The current mirror output flows through a voltage divider and a voltage taken from the divider is supplied as a feedback voltage to the other input of the differential amplifier. The amplifier regulates the load voltage and exhibits a good PSRR, while conserving VPP current.


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patent: 5559687 (

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