Static information storage and retrieval – Powering
Reexamination Certificate
2001-08-28
2002-09-24
Mai, Son (Department: 2818)
Static information storage and retrieval
Powering
C365S185180, C365S185090
Reexamination Certificate
active
06456557
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit (IC) devices, and in particular relates to voltage regulators for IC devices, such as non-volatile memory arrays, that require constant voltage levels over a wide range of processing and operating conditions.
BACKGROUND OF THE INVENTION
FIG. 1
is a simplified schematic diagram showing a portion of a conventional memory device
100
that includes an array
110
of non-volatile memory cells
112
(one shown), a bit line control circuit
120
, and a conventional voltage regulator
130
. Other portions of conventional memory device
100
are omitted for brevity.
According to well-established techniques, the memory cells of array
110
are arranged in rows and columns, and each memory cell
112
is accessed during read, program, or erase operations by applying appropriate voltages to associated word and bit lines. For example, as indicated in
FIG. 1
, the gate terminal of each memory cell
112
is connected to an associated word line WL, and the drain and source terminals of memory cell
112
are connected to associated bit lines BL
1
and BL
2
. Each memory cell of array
110
is addressed using a word line control circuit (not shown) and a bit line control circuit
120
that includes multiplexing circuits (YMUXes)
122
and
124
. Specifically, YMUX
122
includes a series of pass transistors (not shown) that are controlled (turned on and off) by a first set of control signals to connect bit line BL
1
to an appropriate voltage source. Similarly, YMUX
122
includes pass transistors that are controlled to connect bit line BL
2
to ground during a read operation or to a sense amplifier.
During the operational lifetime of each nonvolatile memory cell
112
, it is important that drain voltage Vdrain and gate voltage Vgate be constant over all temperature, system power supply (Vdd) and fabrication process variations (referred to herein as “variable conditions”). Variations of Vdrain produce threshold voltage (Vt) margin loss, which is the difference between the threshold voltage of a programmed cell versus the threshold voltage of an erased cell. When Vt margin loss occurs, the possibility of operational error increases.
Conventional voltage regulator
130
is provided in an attempt to maintain a constant Vdrain during read operations over the variable conditions. Voltage regulator
130
includes an operational amplifier
132
, a PMOS pull-up transistor
134
, a clamp transistor
136
, and a voltage divider
138
. Operational amplifier
132
, PMOS transistor
134
, and voltage divider
138
are connected to generate a reference voltage Vblr that controls the gate voltage of clamp transistor
136
in response to a band gap reference voltage Vbgref, which by definition is constant over the variable conditions and is applied to the inverting input terminal of operational amplifier
132
. The output terminal of operation amplifier
132
is applied to the gate terminal of PMOS transistor
134
, which has a first terminal connected to a first voltage source Vext
1
, thereby causing PMOS transistor
134
to generate reference voltage Vblr. Reference voltage Vblr is passed from the second (lower) terminal of PMOS transistor
134
to the gate terminal of clamp transistor
136
and to voltage divider
138
. Voltage divider
138
includes a first resistor R
1
connected between the second terminal of PMOS transistor
134
and the non-inverting input terminal of operational amplifier
132
, and a second resistor R
2
that is connected between resistor R
1
and ground. Resistors R
1
and R
2
are selected to satisfy the equation: Vblr=Vbgref*(1+R
2
/R
1
). Accordingly, because band gap reference voltage Vbgref is constant over the variable conditions, reference voltage Vblr is also constant over the variable conditions. Clamp transistor
136
, which is controlled by reference voltage Vblr, is connected between a second voltage source Vext
2
and YMUX
122
. Reference voltage Vblr clamps the source voltage of clamp transistor
136
, and passes a reduced voltage (i.e., Vblr−Vgs) through YMUX
122
to the drain of memory cell
112
.
A problem with voltage regulator
130
is that it does not account for resistance variations of pass transistors (not shown) utilized in YMUX
122
that are applied to the drain of memory cell
112
. That is, regardless of the stability of reference voltage Vblr, the resistance of these pass transistors changes in response to variable operating conditions (e.g., temperature) and processing parameters, thereby resulting in potential Vt margin loss because the drain voltage Vdrain applied to memory cell
112
varies widely over the operational lifetime of memory device
100
.
What is needed is voltage regulator for a memory array that compensates for the resistance variations generated in the multiplexing circuit used to access the memory cells of a memory array such that optimal voltage conditions are applied to the memory cells over all process, temperature, and voltage supply variations.
SUMMARY OF THE INVENTION
The present invention is directed to a memory device including a voltage regulator that compensates for resistance variations in the bit line control (multiplexing) circuit used to access the memory cells, thereby providing optimal voltage supply conditions during read operations over all variable conditions. This compensation is achieved by including in the feedback path of the voltage regulator an emulated multiplexing circuit having an identical resistance to that of the multiplexing circuit (or a multiple thereof). This emulated multiplexing circuit is fabricated using the same processing parameters as the multiplexing circuit, and includes the number of series-connected pass transistors that are utilized in the multiplexing circuit to access the memory cells, thereby causing the emulated multiplexing circuit to have an essentially identical resistance to that of the multiplexing circuit over all variable conditions. Accordingly, variations in the resistance of the multiplexing circuit caused by fabrication process variations, system voltage variations, or temperature variations are mirrored in emulated multiplexing circuit, thereby avoiding the Vt margin loss problems associated with conventional voltage regulators.
In accordance with a disclosed embodiment, a voltage regulator of the present invention is incorporated into a memory device including an array of 2-bit non-volatile memory cells. Each 2-bit memory cell has a first charge trapping region for storing a first bit that is read by applying a read voltage to a first terminal and connected the second terminal to ground, and a second charge trapping region for storing a second bit that is read by applying the read voltage to the second terminal and connecting the first terminal to ground. To facilitate this two-way access of each memory cell, a bit line control circuit includes a multi-level multiplexing circuit that selectively passes the read current in either direction through the memory cell. However, such 2-bit memory cells require a very precise drain voltage during read operations that cannot be too great (so as to inadvertently program the non-read bit) or too small (so that the non-read bit influences the read operation). Therefore, even relatively small changes in the variable conditions under which the multiplexing circuit are fabricated and/or operated can cause erroneous read operations. Accordingly, problems associated with the multiplexing circuit used to access 2-bit memory cells are particularly relevant to the present invention. However, the present invention may also be beneficially utilized in memory devices having single-bit memory cells, and also in any other IC devices requiring reliable voltage conditions at nodes accessed through multi-stage accessing circuits.
In the disclosed embodiment, the voltage regulator includes a differential (operational) amplifier, a pull-up transistor, and a feedback path (circuit) including an emulated multiplexing circuit having a resistance that is equ
Dadashev Oleg
Jacob Kyra
Mai Son
Tower Semiconductor LTD
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