Voltage regulator for memory

Static information storage and retrieval – Powering – Data preservation

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S227000, C365S154000

Reexamination Certificate

active

08004924

ABSTRACT:
A circuit includes a first negative feed back loop coupled to a virtual Vvdd power rail and a true Vdd power rail. A second negative feed back loop is coupled to the virtual Vvss power rail and a true Vss power rail. The virtual rail to virtual rail voltage difference is regulated at the highest threshold voltage between pull-up and pull-down transistors of a memory cell.

REFERENCES:
patent: 6584030 (2003-06-01), Marr
patent: 7020041 (2006-03-01), Somasekhar et al.
patent: 7307907 (2007-12-01), Houston
patent: 7366036 (2008-04-01), Cheng et al.
patent: 7808856 (2010-10-01), Ehrenreich et al.
patent: 2005/0243634 (2005-11-01), Liaw
patent: 2007/0252623 (2007-11-01), Zampaglione et al.
patent: 2008/0122415 (2008-05-01), Chou et al.
patent: 2008/0151673 (2008-06-01), Fallah et al.
patent: 2009/0244956 (2009-10-01), Inoue
Khellah, M. M., et al., “A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor”,IEEE Journal of Solid-State Circuits, 42(1), (Jan. 2007), 233-242.
Nii, K, et al., “A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications”,IEEE Journal of Solid-State Circuits, 39(4), (Apr. 2004), 684-693.
Qin, Huifang, et al., “SRAM Leakage Suppression by Minimizing Standby Supply Voltage”,5th International Symposium on Quality Electronic Design(ISQED'04), (2004), 55-60.
Takeyama, Y., et al., “A low leakage SRAM macro with replica cell biasing scheme”,IEEE Journal of Solid-State Circuits, 41(4), (Apr. 2006), 815-822.
Wang, Y, et al., “A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications”,IEEE Journal of Solid-State Circuits, 43(1), (Jan. 2008), 172-179.
Yamaoka, M, et al., “A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor”,IEEE Journal of Solid-State Circuits, 40(1), (Jan. 2005), 186-194.
Zhang, K, et al., “SRAM design on 65nm CMOS technology with integrated leakage reduction scheme”,2004 Symposium on VLSI Circuits, 2004. Digest of Technical Papers., (Jun. 2004), 294-295.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Voltage regulator for memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Voltage regulator for memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage regulator for memory will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2771303

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.