Voltage regulator circuit for suppressing latch-up phenomenon

Details Voltage regulator circuit for suppressing latch-up phenomenon Voltage regulator circuit for suppressing latch-up phenomenon

1999-11-04

2001-02-06

Sterrett, Jeffrey (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S280000, C361S018000

Reexamination Certificate

active

06184664

ABSTRACT:

FIELD OF THE INVENTION
The present invention concerns a voltage regulator circuit for regulating a voltage disturbed by a phenomenon known as <<latch-up>>.
BACKGROUND OF THE INVENTION
Numerous voltage regulator circuits exist in the prior art.
A circuit of this type is disclosed in GB Patent No. 2 298 939, and is shown in
FIG. 1A
of the present description. This circuit includes a control transistor Q
1
connected in series between an input terminal I and an output terminal O, and an output voltage detector D formed of two resistors Ra and Rb connected in series between output terminal O and the circuit's earth.
A voltage corresponding to the output voltage detected by detector D is compared to a reference voltage E
3
by an operational amplifier AO, and the output voltage thereof is applied to the base terminal of a transistor Q
2
. Thus a base current of control transistor Q
1
can be controlled by the output voltage of operational amplifier AO, via transistor Q
2
, so that the impedance of control transistor Q
1
is controlled so as to provide a predetermined voltage at output terminal O.
One problem encountered during the operation of such a circuit lies in the unintentional appearance of phenomena known as <<latch-up>>which occur in an electronic component of the circuit, following external disturbances such as the supply of an electric voltage, an electric current or radiation.
<<Latch-up>>is commonly used to designate any phenomenon occurring in an integrated circuit following external disturbances such as the supply of an electric voltage, an electric current or radiation.
Numerous devices exist in the prior art for detecting <<latch-up>>in a substrate and, in particular, devices analysing a current capable of being disturbed by said phenomenon.
A device of this type is disclosed in Japanese Patent Application No. 5 326 825 in the name of FUNAI ELECTRIC CO LTD, and is shown in
FIG. 1B
of the present description. This device includes an integrated circuit IC
1
at a first terminal of which is provided a supply voltage Vdd, via a bipolar transistor T
1
, and at the second terminal of which is connected a resonant circuit formed of a resistor R
3
and a capacitor C
3
. A detection integrated circuit IC
2
includes an earth terminal, a first terminal at which is provided supply voltage Vdd, and a second terminal connected to said resonant circuit as well as to the base terminal of a bipolar transistor T
2
via a resistor R
2
. The base terminal of transistor T
1
is connected to the collector terminal of transistor T
2
via a resistor R
1
, and the emitter terminal of transistor T
2
is earthed.
In the device described hereinbefore in relation to
FIG. 1B
, if latch-up occurs, a significant drop in supply voltage Vdd is detected by integrated circuit IC
2
. In this case, transistors T
1
and T
2
are blocked, and the voltage supplying integrated circuit IC
1
is interrupted, which initialises the circuit. Subsequently, integrated circuit IC
1
again operates normally.
However, these devices have complex structures and require a large number of electronic components to perform the detection and regulator functions.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a voltage regulator circuit intended to suppress any inadvertent latch-up phenomenon.
Another object of the present invention is to provide a circuit of this type which answers criteria as to cost and simplicity.
These objects, in addition to others are achieved by the voltage regulator circuit according to claim
1
.
One advantage of the circuit according to the present invention is that it provides a voltage regulator circuit having a structure not very complex which makes it cheap.
Another advantage of the circuit according to the present invention is that it provides a circuit including voltage comparison means to the input of which is supplied the regulated voltage, these means being arranged so as to define two voltage thresholds capable of being predetermined to respond to the needs of the user.
These objects, features and advantages of the present invention, in addition to others will appear more clearly upon reading the detailed description of a preferred embodiment of the invention, given solely by way of example, with reference to the annexed drawings:


REFERENCES:
patent: 3217237 (1965-11-01), Giger
patent: 5177429 (1993-01-01), Eki
patent: 5212616 (1993-05-01), Dhong et al.
patent: 2 298 939 (1996-03-01), None
Prediger et al., “Bipolare Konstantstromquelle”, vol. 42, No. 21, Oct. 19, 1993, p. 132/133.
Chambers, A.S., “Programmable D.C. Power Supplies”, Industrial Electronics, Dec. 1968, pp. 480-483.
Vittoz et al., “CMOS Analog Integrated Circuits Based on Weak Inversion Operation”, IEEE Jour. of Solid-State, vol. SC-12, No. 3, Jun. 1977, pp. 224-231.
Degrauwe et al., “CMOS Voltage References Using Lateral Bipolar Transistors”, IEEE, Jour. of Solid-State, vol. SC-20, No. 6, Dec. 1985.

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