Voltage regulator

Details Voltage regulator Voltage regulator

2007-03-20

2007-03-20

Berhane, Adolf (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

Reexamination Certificate

active

11406330

ABSTRACT:
Consumption current is reduced for a voltage regulator in sleep mode. In normal operation mode, a sub-regulator circuit is ceased from operating according to a power-down signal, which allows an operation amplifier to compare between a reference voltage outputted from a reference voltage circuit and a monitor voltage generated by a voltage-dividing circuit. Based on a detection voltage as a comparison result, a PMOS is controlled to regulate an internal power voltage such that the monitor voltage becomes equal to the reference voltage. In sleep mode, the reference voltage circuit and operational amplifier is ceased from operating, to start up the sub-regulator circuit. A slight current, restricted by a resistance, flows through a PMOS of the sub-regulator circuit. The same magnitude of current is supplied from the PMOS constituting a current mirror to a PMOS, etc. of a threshold-voltage output circuit. The threshold voltage, at a node between the PMOS constituting the current mirror and the PMOS of the threshold-voltage output circuit, is power-amplified by a voltage follower and outputted through an output terminal.

REFERENCES:
patent: 6806694 (2004-10-01), Rupp et al.
patent: 7002329 (2006-02-01), Agari et al.
patent: 7030596 (2006-04-01), Salerno et al.
patent: 7071660 (2006-07-01), Xu et al.
patent: 2001-211640 (2001-08-01), None

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