Voltage regulation and latch-up protection circuits

Details Voltage regulation and latch-up protection circuits Voltage regulation and latch-up protection circuits

1991-10-23

1993-05-18

Pellinen, A. D.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Voltage regulator protective circuits

361 58, 361 88, H02H 710

Patent

active

052126161

ABSTRACT:
An improved latch-up protection circuit is disclosed which prevents damage to a CMOS integrated circuit chip due to transient surges or internal-circuitry initiated latch-ups and which clears any latch-up condition or SCR mode. In each embodiment, the latch-up protection circuit is integrated with an on-chip voltage regulation circuit which provides on-chip power to the internal chip circuitry. A first approach to implementing the latch-up protection circuit is to detect an average current through the power transistor of the voltage regulation circuit over a few microseconds. Should the average current exceed a preset value, then the power transistor is turned off and the power (V.sub.DDI) supplied to the internal chip circuitry is reduced to zero, thereby removing the latch-up condition. In a second approach, the on-chip voltage (V.sub.DDI) supplied to internal chip circuitry is compared with a reference voltage signal representative of the occurrence of a latch-up condition, i.e., with the nominal external power supply. When the on-chip power supply voltage V.sub.DDI becomes lower than the trigger voltage, then the power transistor and voltage regulation circuit is disabled, thereby reducing the latch-up condition. Both CMOS and NMOS implementations of the combination voltage regulation and latch-up protection circuit are disclosed.

REFERENCES:
patent: 4008418 (1977-02-01), Murphy
patent: 4021701 (1977-05-01), Davies
patent: 4547828 (1985-10-01), Bloomer
patent: 4594633 (1986-06-01), Townsend et al.
patent: 4723081 (1988-02-01), Akatsuka
patent: 4731574 (1988-03-01), Melbert
patent: 4761702 (1988-08-01), Pinard
Zappe, H. P., "Switchable Power Supply to Prevent Latchup Damage to CMOS Integrated Circuits", IBM Technical Disclosure Bulletin, vol. 27, No. 9, pp. 5038-5040, 1985.

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