Static information storage and retrieval – Floating gate – Particular biasing
Patent
1999-06-08
2000-02-08
Fears, Terrell W.
Static information storage and retrieval
Floating gate
Particular biasing
365226, 36518902, 36523002, G11C 1134
Patent
active
06023427&
ABSTRACT:
A standard single well (e.g., n-well) complementary metal-oxide-semiconductor (CMOS) process compatible voltage pump switch routes -10 Volt for erasing a floating gate transistor when an IC substrate is grounded at 0 Volts. The voltage pump switch also routes extreme positive voltages for programming or reading the floating gate transistor. P-channel field-effect transistors (PFETs) multiplex both the read/write/programming and erasing voltages, such as in a block-erasable flash electrically erasable and programmable read only memory (EEPROM). The voltage pump switch includes a charge pump for providing to the PFET routing the erasing voltage a gate voltage that is more negative than the erasing voltage by the PFET turn-on threshold voltage (V.sub.T) magnitude.
REFERENCES:
patent: 5212442 (1993-05-01), O'Toole et al.
patent: 5313429 (1994-05-01), Chevallier et al.
patent: 5619459 (1997-04-01), Gilliam
Dipert, B., et al., "Flash Memory Goes Mainstream", IEEE Spectrum, 30, 48-52, (1993).
Chevallier Christophe J.
Lakhani Vinod
Fears Terrell W.
Micro)n Technology, Inc.
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