Voltage multiplier with improved efficiency

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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C363S059000, C363S060000

Reexamination Certificate

active

07602233

ABSTRACT:
A multi-stage voltage multiplication circuit and methodology are provided which use a multi-stage charge pump boosting circuit (210) and two-stage pass gate circuit (220) having complementary power switches (M6, M9, M7, M10) to efficiently develop an output voltage (VOUT) that is higher than the input supply voltage (VDD). By using a two-stage complementary switch to connect boosted clock signals (P1, P2) from a charge pump (210) to the multiplier output (VOUT), return current from the storage capacitor (COUT) to the pumping capacitor (C1, C2) is blocked, thereby increasing power transfer efficiency, even at high clock frequencies. In addition, a boosted auxiliary voltage is generated by an additional boosting stage (230) and applied to the PMOS wells of the pass gate circuit (220), thereby preventing latch-up and backflow.

REFERENCES:
patent: 5493486 (1996-02-01), Connell et al.
patent: 6975161 (2005-12-01), Yen
patent: 2005/0024125 (2005-02-01), McNitt et al.
patent: 2005/0195017 (2005-09-01), Chen et al.
P. Favrat et al., A High Efficiency CMOS Voltage Doubler, IEEE Journal of Solid-State Circuits, vol. 33, No. 3, Mar. 1988.

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